aclink3.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aclink3 is
		PORT(
		bit_clk	,key1,sdata_in: IN	STD_LOGIC;
		sl:buffer std_logic;
		slot :buffer std_logic_vector(3 downto 0);
		outdata:buffer std_logic_vector(19 downto 0);
		sync	: OUT	STD_LOGIC;
		slot0data:out std_logic_vector(15 downto 0);
		slot1data:out std_logic_vector(19 downto 0);
		slot2data:out std_logic_vector(19 downto 0);
		slot3data:out std_logic_vector(19 downto 0);
		slot4data:out std_logic_vector(19 downto 0);
		slot5data:out std_logic_vector(19 downto 0);
		slot6data:out std_logic_vector(19 downto 0);
		slot7data:out std_logic_vector(19 downto 0);
		slot8data:out std_logic_vector(19 downto 0);
		slot9data:out std_logic_vector(19 downto 0);
		slot10data:out std_logic_vector(19 downto 0);
		slot11data:out std_logic_vector(19 downto 0);
		slot12data:out std_logic_vector(19 downto 0)
		);
END aclink3;
architecture behav of aclink3 is
signal play_sig1:std_logic;
component sreg3
port(sl,clk,q:in std_logic;
	dataout:out std_logic_vector(19 downto 0));
end component;
begin
u1:sreg3 port map(sl,bit_clk,sdata_in,outdata);
process(bit_clk)
variable counter: std_logic_vector(7 downto 0);
begin
if(bit_clk'event and bit_clk='1')then
if(play_sig1='1')then
if(conv_integer(counter)<16)then
sync<='1';
counter:=counter+1;
else
counter:=counter+1;
sync<='0';
end if;
if(counter<2)then
slot<="1100";
elsif(counter<18)then
slot<="0000";
elsif(counter<38)then
slot<="0001";
elsif(counter<58)then
slot<="0010";
elsif(counter<78)then
slot<="0011";
elsif(counter<98)then
slot<="0100";
elsif(counter<118)then
slot<="0101";
elsif(counter<138)then
slot<="0110";
elsif(counter<158)then
slot<="0111";
elsif(counter<178)then
slot<="1000";
elsif(counter<198)then
slot<="1001";
elsif(counter<218)then
slot<="1010";
elsif(counter<238)then
slot<="1011";
else
slot<="1100";
end if;
if(counter=2)then
sl<='0';
elsif(counter=18)then
sl<='0';
elsif(counter=38)then
sl<='0';
elsif(counter=58)then
sl<='0';
elsif(counter=78)then
sl<='0';
elsif(counter=98)then
sl<='0';
elsif(counter=118)then
sl<='0';
elsif(counter=138)then
sl<='0';
elsif(counter=158)then
sl<='0';
elsif(counter=178)then
sl<='0';
elsif(counter=198)then
sl<='0';
elsif(counter=218)then
sl<='0';
elsif(counter=238)then
sl<='0';
else
sl<='1';
end if;
end if;
end if;
end process;
process(key1)
begin
if(key1'event and key1='0')then
	play_sig1<=not play_sig1;
end if;
end process;
process(outdata)
begin
case slot is
when "0000"=>slot12data<=outdata;
when "0001"=>slot0data<=outdata(15 downto 0);
when "0010"=>slot1data<=outdata;
when "0011"=>slot2data<=outdata;
when "0100"=>slot3data<=outdata;
when "0101"=>slot4data<=outdata;
when "0110"=>slot5data<=outdata;
when "0111"=>slot6data<=outdata;
when "1000"=>slot7data<=outdata;
when "1001"=>slot8data<=outdata;
when "1010"=>slot9data<=outdata;
when "1011"=>slot10data<=outdata;
when "1100"=>slot11data<=outdata;
when others=>slot0data<="0000000000000000";
			slot1data<="00000000000000000000";
			slot2data<="00000000000000000000";
			slot3data<="00000000000000000000";
			slot4data<="00000000000000000000";
			slot5data<="00000000000000000000";
			slot6data<="00000000000000000000";
			slot7data<="00000000000000000000";
			slot8data<="00000000000000000000";
			slot9data<="00000000000000000000";
			slot10data<="00000000000000000000";
			slot11data<="00000000000000000000";
			slot12data<="00000000000000000000";
end case;
end process;
end behav;