rxd3.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

--v1.0 rxd databit 8  none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
	sig1:buffer std_logic;
			q:out std_logic_vector(7 downto 0));
end rxd3;
architecture behav of rxd3 is
signal tmpreg8:std_logic_vector(8 downto  0);
signal sig2:integer range 0 to 16;--接收时钟计数
signal sig3:integer range 0 to 9;--接受数据位数
signal sig4:std_logic;--sig4串并变换时钟
begin
process(clk)
	begin
		if(clk'event and clk='0')then
			if(sig1='0')then--ri状态
				if(rx='0')then--此if语句用于判断是否起始位，是则sig1置位‘1’
					if(sig2=7)then--对应于起始位的处理
						sig2<=0;
						sig1<='1';
						sig4<='1';
					else 
						sig2<=sig2+1;
						sig4<='0';
					end if;
				else
					sig2<=0;
				end if;
			else--ri为‘1’，接收数据
				if(sig2=15)then--对应于数据位的处理
					sig2<=0;
					if(sig3=8)then--接收完一帧否？若接收完，则sig1置‘0’
						sig3<=0;
						sig1<='0';
						sig4<='0';
					else
						sig3<=sig3+1;
						sig4<='1';
					end if;
					

				else
					
					sig2<=sig2+1;
					sig4<='0'; 
				end if;
			end if;
		end if;
		
				

		
end process;



process(sig4)--此过程完成接收数据的串并变换
	begin

		if (sig4'event)and(sig4='1') then

			for i in tmpreg8'high downto tmpreg8'low+1 loop
			tmpreg8(i)<=tmpreg8(i-1);
			end loop;
			tmpreg8(tmpreg8'low)<=rx;
		end if;
		
end process;
process
begin
	for i in 7 downto 0 loop 
		q(i)<=tmpreg8(i);
	end loop;
	
end process;

end behav;