scan_gen.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

package test_con is
	constant N1:integer:=3686;
end test_con;
use work.test_con.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity scan_gen is
port(clkin :in std_logic;
		clkout :out std_logic);
end scan_gen;
architecture rtl of scan_gen is
component fredivn is
	GENERIC (N:positive);
port (clk:in std_logic;
		outclk:out std_logic);
end component;
begin
u1:fredivn
	generic map(N=>N1)
	port map(clkin,clkout);
end rtl;