dff2.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff2 is
	port(clk,cd,sd,d:in std_logic;
				q,notq:out std_logic);
end dff2;
architecture rtl of dff2 is
begin 
	process(clk,sd,cd)
		begin
			if(cd='0')then
			q<='0';
			notq<='1';
			elsif (sd='0')then
			q<='1';
			notq<='0';
			else
			if((clk'event) and (clk='1') )then
					q<=d;
			end if;
			end if;
	end process;
end rtl;