fredivn.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fredivn is
	GENERIC (N:integer:=8);
port (clk:in std_logic;
		outclk:out std_logic);
end fredivn;

architecture rtl of fredivn is
signal count:integer;
begin
process(clk)
begin 
	if(clk'event and clk='1') then
	if(count=N-1)then
			count<=0;
	else
	
			count<=count+1;
		if count<(integer(N/2)) then
			outclk<='0';
		else
			outclk<='1';
		end if;
	end if;
	end if;
end process;
end rtl;