codetran.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity codetran is
port(scan_code :in std_logic_vector(7 downto 0);
	clk:in std_logic;
	key_code:out std_logic_vector(7 downto 0));
end codetran;
architecture behav of codetran is
begin
process(clk)
begin
if(clk'event and clk='1')then
case scan_code is
when "11101110"=>key_code<="00000000";
when "11101101"=>key_code<="00000001";
when "11101011"=>key_code<="00000010";
when "11100111"=>key_code<="00000011";
when "11011110"=>key_code<="00000100";
when "11011101"=>key_code<="00000101";
when "11011011"=>key_code<="00000110";
when "11010111"=>key_code<="00000111";
when "10111110"=>key_code<="00001000";
when "10111101"=>key_code<="00001001";
when "10111011"=>key_code<="00001010";
when "10110111"=>key_code<="00001011";
when "01111110"=>key_code<="00001100";
when "01111101"=>key_code<="00001101";
when "01111011"=>key_code<="00001110";
when "01110111"=>key_code<="00001111";
when others    =>key_code<="11111111";
end case;
end if;
end process;
end behav;