keyboard.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keyboard is
port(clk:in std_logic;
		row:in std_logic_vector(3 downto 0);
		com:out std_logic_vector(3 downto 0);
		key_code:out std_logic_vector(7 downto 0));
end keyboard;
architecture rtl of keyboard is
signal clk1,key_pre:std_logic;
signal scan_code:std_logic_vector(7 downto 0);
COMPONENT scan_gen
		port(clkin :in std_logic;
		clkout :out std_logic);
END COMPONENT;
COMPONENT key_press
		port(clk1:in std_logic;
		row:in std_logic_vector(3 downto 0);
		key_pre:out std_logic);
END COMPONENT;
COMPONENT key_scan
		port(clk,key_pre:in std_logic;
		row:in std_logic_vector(3 downto 0);
		com:out std_logic_vector(3 downto 0);
		scan_code:out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT codetran
		port(scan_code :in std_logic_vector(7 downto 0);
	clk:in std_logic;
	key_code:out std_logic_vector(7 downto 0));
END COMPONENT;
begin
u1:scan_gen
port map(clk,clk1);
u2:key_press
port map(clk1,row,key_pre);
u3:key_scan
port map(clk,key_pre,row,com,scan_code);
u4:codetran 
port map(scan_code,clk,key_code);
end rtl;