opt.vhd

来自「《CPLD/FPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 35 行

IF clear='1' THEN
      cnt<=0;
 ELSE
 IF (clkf'EVENT AND clkf='1') THEN
         IF cnt=15 THEN
             cnt<=1;
         ELSE
            cnt<=cnt+1;
        END IF;
    END IF;
 END IF;
 IF cnt=1 THEN
  outv:='1';
 ELSE
  outv:='0';
 END IF;
outb<=outv;
--
IF clear='1' THEN
 cnt<=0;
 ELSE
     IF (clkf'EVENT AND clkf='1') THEN

          IF cnt=15 THEN
              cnt<=1;
              outb <= '1';
          ELSE
              cnt<=cnt+1;
              outb <= '0';
          END IF;
     END IF;
END IF;
outb<=outv;