reg8.vhd

来自「《CPLD/FPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 24 行

Library IEEE ;
use IEEE.std_logic_1164.all ;


ENTITY reg8 IS
	PORT(
		d_1:in std_logic_vector(3 downto 0);
		d_2:in std_logic_vector(3 downto 0);
		clk: IN   std_logic;
		q_1:out std_logic_vector(3 downto 0);
		q_2:out std_logic_vector(3 downto 0));
END reg8;

ARCHITECTURE a OF reg8 IS
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL clk = '1';
		q_1<= d_1;
		q_2<= d_2;
	END PROCESS;
END a;