clk.vhd

来自「《CPLD/FPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk is
port( 
       clk  :   in std_logic;
    address :   out std_logic_vector(5 downto 0));
end clk;

architecture behave of clk is
begin
   process(clk)
   variable count : std_logic_vector(5 downto 0);
   begin
       wait until clk'event and clk='0';
       count:=count+1;
       address<=count;
   end process;
end behave;