📄 platform.h
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#define OMAHA_INT_SPI 22#define OMAHA_INT_URXD0 23#define OMAHA_INT_URXD1 24#define OMAHA_INT_USBD 25#define OMAHA_INT_USBH 26#define OMAHA_INT_IIC 27#define OMAHA_INT_UTXD0 28#define OMAHA_INT_UTXD1 29#define OMAHA_INT_RTC 30#define OMAHA_INT_ADC 31/* ----------------------------------------------------------------------- * PLD Control registers (offset from PLAT_PLD_BASE) * ----------------------------------------------------------------------- *//* register offsets from PLAT_PLD_BASE */#define PLD_FPGA_ID 0x00 /* 8-bit FPGA ID number (ro) */#define PLD_INT_CTRL 0x04 /* Interrupt control */#define PLD_INT_STATUS 0x08 /* Interrupt status */#define PLD_WAIT_STATUS 0x0C /* IO device wait status */#define PLD_ID 0x10 /* PCB revision number */#define PLD_BUS 0x14 /* Expansion bus control register */#define PLD_TEST 0x18 /* 8-bit test register (rw) */#define PLD_CF 0x1C /* CompactFlash control */#define PLD_DMA_CTRL 0x20 /* DMA Control register *//* PLD Register bitdefs *//* PLD_FPGA_ID ; contains FPGA Iden *//* INT_CTRL bit-defs */#define PLD_INT_CTRL_USB BIT0 /* USB */#define PLD_INT_CTRL_LAN BIT1 /* Ethernet *//* INT_STATUS bit-defs */#define PLD_INT_STATUS_CF_IDE BIT0 /* CF True-IDE mode (r/w) */#define PLD_INT_STATUS_nDATACS BIT1 /* SMC91C111 nDATACS control (r/w) */#define PLD_INT_STATUS_CF_RDY BIT2 /* CompactFlash ready (r/o) */#define PLD_INT_STATUS_nWP BIT3 /* Flash write protect (r/w) *//* WAIT_STATUS bit-defs */#define PLD_WAIT_STATUS_USB BIT0 /* USB wait signal active */#define PLD_WAIT_STATUS_LAN BIT1 /* Ethernet wait signal active */#define PLD_WAIT_STATUS_CF BIT2 /* CompactFlash wait status *//* ID ; Contains PLD Id *//* BOARD_ADDR */#define PLD_BUS_ADDR 0x0F /* 4-bit expansion bus address */#define PLD_BUS_nACK BIT4 /* BUS nACK */#define PLD_BUS_nCLR BIT5 /* BUS nCLR */#define PLD_BUS_nSTR BIT6 /* BUS nSTR */#define PLD_BUS_DONE BIT7 /* BUS Done *//* TEST ; 8-bit r/w any value. *//* CF status bitdefs */#define PLD_CF_WP BIT0 /* r/w */#define PLD_CF_RDY BIT1 /* CF_RDY r/o */#define PLD_CF_VS1 BIT2 /* Voltage Sense 1. r/o */#define PLD_CF_VS2 BIT3 /* Voltage Sense 2. r/o */#define PLD_CF_RESET BIT4 /* Reset. r/w (TrueIDE active low/else high) */#define PLD_CF_CD BIT5 /* Card Detect (1 AND 2). r/o */#define PLD_CF_BVD BIT6 /* Batt. Voltage Detect (1 AND 2). r/o */#define PLD_CF_nINPACK BIT7 /* Input Acknowlegde. r/o *//* DMA_CTRL */#define PLD_DMA_BUS BIT4 /* Bus DMA request. r/w */#define PLD_DMA_USB BIT5 /* USB DMA request. r/w */#define PLD_DMA_FPGA BIT6 /* FPGA DMA request. r/w *//* ======================================================================= * Start of uHAL definitions * ======================================================================= */#define MAXIRQNUM 31 #define NR_IRQS (MAXIRQNUM + 1)/* ----------------------------------------------------------------------- * LEDs - One available * ----------------------------------------------------------------------- * */#define uHAL_LED_ON 1#define uHAL_LED_OFF 0#define uHAL_NUM_OF_LEDS 4/* Colours may not match reality... */#define GREEN_LED BIT8#define YELLOW_LED BIT9#define RED_LED BIT10#define RED_LED_1 BIT11#define ALL_LEDS (RED_LED | RED_LED_1 | YELLOW_LED | GREEN_LED) #define LED_BANK PLAT_DBG_LEDS/* LED definitions. * The bit patterns & base addresses of the individual LEDs */#define uHAL_LED_MASKS {0, GREEN_LED, YELLOW_LED, RED_LED, RED_LED_1}#define uHAL_LED_OFFSETS {0, (void *)LED_BANK, (void *)LED_BANK, (void *)LED_BANK}/* ----------------------------------------------------------------------- * Memory definitions - run uHAL out of SDRAM. Reserve top 64K for MMU. */#define uHAL_MEMORY_SIZE PLAT_USER_SDRAM_SIZE/* Application Flash */#define FLASH_BASE PLAT_FLASH_BASE#define WFLASH_BASE PLAT_FLASH_UNCACHED#define FLASH_SIZE PLAT_FLASH_SIZE#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)#define FLASH_BLOCK_SIZE SZ_4K/* Reserve the first sector of flash for the boot switcher. * Note: Changes to PLAT_BOOT_ROM_HI will have to be reflected in * FlashLibrary/Boards/P920/flashMap.h */#define PLAT_BOOT_ROM_HI FLASH_BASE#define PLAT_BOOT_ROM_SIZE (FLASH_BLOCK_SIZE*0)/* Boot Flash */#define EPROM_BASE PLAT_BOOT_ROM_HI#define EPROM_SIZE PLAT_BOOT_ROM_SIZE#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)/* Clean base - an area of memory (usually fast access) which can be read * to ensure the data caches are flushed. */#define CLEAN_BASE EPROM_BASE/* ----------------------------------------------------------------------- * UART definitions *//* Which com port can the OS use? * *//* Default port to talk to host (via debugger) */#define HOST_COMPORT OMAHA_UART0_BASE#define HOST_IRQBIT_NUMBER OMAHA_INT_URXD0#define HOST_IRQBIT (1 << HOST_IRQBIT_NUMBER)/* Default port for use by Operating System or program */#define OS_COMPORT OMAHA_UART0_BASE#define OS_IRQBIT_NUMBER OMAHA_INT_URXD0#define OS_IRQBIT (1 << OS_IRQBIT_NUMBER)#define DEBUG_COMPORT OS_COMPORT#define DEBUG_IRQBIT OS_IRQBIT/* Values to set given baud rates */#define DEFAULT_HOST_BAUD ARM_BAUD_9600#define DEFAULT_OS_BAUD ARM_BAUD_38400/* 'C' macros to access comports */#define GET_STATUS(p) (IO_READ((p) + OMAHA_UTRSTAT))#define GET_CHAR(p) ((IO_READ((p) + OMAHA_URXH)) & 0xFF)#define PUT_CHAR(p, c) (IO_WRITE(((p) + OMAHA_UTXH), (c)))#define IO_READ(p) (*(volatile unsigned int *)(p))#define IO_WRITE(p, c) (*(unsigned int *)(p) = (c))#define IO_MASK_WRITE(p, m, c) IO_WRITE(p, (IO_READ(p) & ~(m)) | (c))#define IO_SET(p, c) IO_WRITE(p, (IO_READ(p) | (c)))#define IO_CLEAR(p, c) IO_WRITE(p, (IO_READ(p) & ~(c)))#define RX_DATA(s) (((s) & OMAHA_URX_FULL))#define TX_READY(s) (((s) & OMAHA_UTX_EMPTY))#define TX_EMPTY(p) ((GET_STATUS(p) & OMAHA_UTX_EMPTY) != 0)/* ----------------------------------------------------------------------- * Timer definitions * * There are 5 16-bit countdown timers on-chip. * These are all driven by PCLK, running at whatever Mhz. * For now we shall clock all the timers at 1MHz (arranged by uHAL) */#define PLAT_TIMER1_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB0)#define PLAT_TIMER2_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB1)#define PLAT_TIMER3_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB2)#define PLAT_TIMER4_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB3)#define PLAT_TIMER5_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB4)#define MAX_TIMER 5/* Maximum time interval we can handle (in microseconds) * = max_ticks / ticks_per_us ( = 65535 / 0.2) *//* Maximum period in uSecs */#define MAX_PERIOD 131072 #define PLAT_uS_TO_TICK(t) (t*1)/* These are useconds NOT ticks. */#define mSEC_1 1000#define mSEC_5 (mSEC_1 * 5)#define mSEC_10 (mSEC_1 * 10)#define mSEC_25 (mSEC_1 * 25)#define SEC_1 (mSEC_1 * 1000)/* SEMIHOSTED Debugger doesn't use a timer by default. If it requires a * timer (eg for profiling), set HOST_TIMER to MAX_TIMER */#define HOST_TIMER 0#define OS_TIMER 1#define OS_TIMERINT OMAHA_INT_TIMER1/* Timer definitions. * The irq numbers & base addresses of the individual timers */#define TIMER_VECTORS {0, OMAHA_INT_TIMER0, OMAHA_INT_TIMER1, OMAHA_INT_TIMER2, OMAHA_INT_TIMER3, OMAHA_INT_TIMER4}#define TIMER_BASES {0, (void *)PLAT_TIMER1_BASE, (void *)PLAT_TIMER2_BASE, (void *)PLAT_TIMER3_BASE, (void *)PLAT_TIMER4_BASE, (void *)PLAT_TIMER5_BASE}/* ----------------------------------------------------------------------- * Number of Level2 table entries in uHAL_AddressTable * Each entry contains 256 32-bit descriptors */#define L2_TABLE_ENTRIES 0/* macros to map from PCI memory/IO addresses to local bus addresses */#define _MapAddress(a) (a)#define _MapIOAddress(a) (a)#define _MapMemAddress(a) (a)#define ALLBITS 0xffffffff#ifdef uHAL_HEAP#if USE_C_LIBRARY != 0#define uHAL_HEAP_BASE (PLAT_SDRAM_BASE + SZ_1M)#define uHAL_HEAP_SIZE (SZ_16M - SZ_1M - SZ_1M - 4)#define uHAL_STACK_BASE SZ_16M#define uHAL_STACK_SIZE SZ_1M#else#define uHAL_HEAP_BASE (PLAT_SDRAM_BASE + PLAT_SDRAM_SIZE - SZ_64K)#define uHAL_HEAP_SIZE SZ_16K#define uHAL_STACK_SIZE SZ_16K#define uHAL_STACK_BASE (uHAL_HEAP_BASE + SZ32K)#endif#endif#endif/* END */⌨️ 快捷键说明
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