platform.h

一个2.4.21版本的嵌入式linux内核

/*  PWM Timers
 */
#define OMAHA_TCFG0                     0x1100000	 /*  Timer 0 config */
#define OMAHA_TCFG1                     0x1100004	 /*  Timer 1 config */
#define OMAHA_TCON                      0x1100008	 /*  Timer control */
#define OMAHA_TCNTB0                    0x110000C	 /*  Timer count buffer 0 */
#define OMAHA_TCMPB0                    0x1100010	 /*  Timer Compare buffer 0 */
#define OMAHA_TCNTO0                    0x1100014	 /*  Timer count observation 0 */
#define OMAHA_TCNTB1                    0x1100018	 /*  Timer count buffer 1 */
#define OMAHA_TCMPB1                    0x110001C	 /*  Timer compare buffer 1 */
#define OMAHA_TCNTO1                    0x1100020	 /*  Timer count observation 1 */
#define OMAHA_TCNTB2                    0x1100024	 /*  Timer count buffer 2 */
#define OMAHA_TCMPB2                    0x1100028	 /*  Timer compare buffer 2 */
#define OMAHA_TCNTO2                    0x110002C	 /*  Timer	count observation 2 */
#define OMAHA_TCNTB3                    0x1100030	 /*  Timer count buffer 3 */
#define OMAHA_TCMPB3                    0x1100034	 /*  Timer compare buffer 3 */
#define OMAHA_TCNTO3                    0x1100038	 /*  Timer	count observation 3 */
#define OMAHA_TCNTB4                    0x110003C	 /*  Timer count buffer 2 */
#define OMAHA_TCNTO4                    0x1100040	 /*  Timer	count observation 2 */

/*  DMA
 */
#define OMAHA_DMA_CON                   0x12001C0	 /*  DMA Interface control */
#define OMAHA_DMA_UNIT                  0x12001C4	 /*  DMA Transfer unit counter */
#define OMAHA_DMA_FIFO                  0x12001C8	 /*  DMA Transfer FIFO counter */
#define OMAHA_DMA_TX                    0x12001CC	 /*  DMA Total transfer counter */

/*  Watchdog
 */
#define OMAHA_WTCON                     0x1300000	 /*  Watchdog control register */
#define OMAHA_WTDAT                     0x1300004	 /*  Watchdog data */
#define OMAHA_WTCNT                     0x1300008	 /*  Watchdog count */
#define OMAHA_WT_DEF                    0x0		 /*  Disable the watchdog */

/*  IIC
 */
#define OMAHA_IICCON                    0x1400000	 /*  IIC Control */
#define OMAHA_IICSTAT                   0x1400004	 /*  IIC Status */
#define OMAHA_IICADD                    0x1400008	 /*  IIC address */
#define OMAHA_IICDS                     0x140000C	 /*  IIC Data shift */

/*  IIS
 */
#define OMAHA_IISCON                    0x1508000	 /*  IIS Control */
#define OMAHA_IISMOD                    0x1508004	 /*  IIS Mode */
#define OMAHA_IISPSR                    0x1508008	 /*  IIS Prescaler */
#define OMAHA_IISFIFOCON                0x150800C	 /*  IIS FIFO control */
#define OMAHA_IISFIF                    0x1508010	 /*  IIS Fifo entry */

/*  I/O Ports (GPIO's)
 */
#define OMAHA_PACON                     0x1600000	 /*  Port A control */
#define OMAHA_PADAT                     0x1600004	 /*  Port A data */
#define OMAHA_PBCON                     0x1600008	 /*  Port B control */
#define OMAHA_PBDAT                     0x160000C	 /*  Port B data */
#define OMAHA_PBUP                      0x1600010	 /*  Port B pull-up control */
#define OMAHA_PCCON                     0x1600014	 /*  Port C control */
#define OMAHA_PCDAT                     0x1600018	 /*  Port C data */
#define OMAHA_PCUP                      0x160001C	 /*  Port C pull-up */
#define OMAHA_PDCON                     0x1600020	 /*  Port D control */
#define OMAHA_PDDAT                     0x1600024	 /*  Port D data */
#define OMAHA_PDUP                      0x1600028	 /*  Port D pull-up */
#define OMAHA_PECON                     0x160002C	 /*  Port E control */
#define OMAHA_PEDAT                     0x1600030	 /*  Port E data */
#define OMAHA_PEUP                      0x1600034	 /*  Port E pull-up */
#define OMAHA_PFCON                     0x1600038	 /*  Port F control */
#define OMAHA_PFDAT                     0x160003C	 /*  Port F data */
#define OMAHA_PFUP                      0x1600040	 /*  Port F pull-up */
#define OMAHA_PGCON                     0x1600044	 /*  Port G control */
#define OMAHA_PGDAT                     0x1600048	 /*  Port G data */
#define OMAHA_PGUP                      0x160004C	 /*  Port G pull-up */
#define OMAHA_OPENCR                    0x1600050	 /*  Open Drain enable */
#define OMAHA_MISCCR                    0x1600054	 /*  Misc. control */
#define OMAHA_EXTINT                    0x1600058	 /*  External interrupt control */

/*  RTC
 */
#define OMAHA_RTCCON                    0x1700040	 /*  RTC Control */
#define OMAHA_TICINT                    0x1700044	 /*  Tick time count */
#define OMAHA_RTCALM                    0x1700050	 /*  RTC Alarm control */
#define OMAHA_ALMSEC                    0x1700054	 /*  Alarm Second */
#define OMAHA_ALMMIN                    0x1700058	 /*  Alarm Minute */
#define OMAHA_ALMHOUR                   0x170005C	 /*  Alarm Hour */
#define OMAHA_ALMDAY                    0x1700060	 /*  Alarm Day */
#define OMAHA_ALMMON                    0x1700064	 /*  Alarm Month */
#define OMAHA_ALMYEAR                   0x1700068	 /*  Alarm Year */
#define OMAHA_RTCRST                    0x170006C	 /*  RTC Round Reset */
#define OMAHA_BCDSEC                    0x1700070	 /*  BCD Second */
#define OMAHA_BCDMIN                    0x1700074	 /*  BCD Minute */
#define OMAHA_BCDHOUR                   0x1700078	 /*  BCD Hour */
#define OMAHA_BCDDAY                    0x170007C	 /*  BCD Day */
#define OMAHA_BCDDATE                   0x1700080	 /*  BCD Date */
#define OMAHA_BCDMON                    0x1700084	 /*  BCD Month */
#define OMAHA_BCDYEAR                   0x1700088	 /*  BCD Year */

/*  ADC
 */
#define OMAHA_ADCCON                    0x1800000	 /*  ADC control */
#define OMAHA_ADCDAT                    0x1800004	 /*  ADC data */

/*  SPI
 */
#define OMAHA_SPCON                     0x1900000	 /*  SPI Control */
#define OMAHA_SPSTA                     0x1900004	 /*  SPI status */
#define OMAHA_SPPIN                     0x1900008	 /*  SPI pin control */
#define OMAHA_SPPRE                     0x190000C	 /*  Baud rate prescaler */
#define OMAHA_SPTDAT                    0x1900010	 /*  SPI Tx data */
#define OMAHA_SPRDAT                    0x1900014	 /*  SPI Rx data */

/*  MMC
 */

/*  Memory timings
 */

/*  nGCS0: 8-bit r/o, no-wait. boot flash
 *  nGCS1: 32-bit, r/w, no-wait. PLD (inc. ethernet)
 *  nGCS2: 16-bit, r/w, wait. CompactFlash+USB2
 *  nGCS3: 32-bit, r/w, no-wait. FPGA
 *  nGCS4: 32-bit, r/w, no-wait. Expansion Bus
 *  nGCS5: 32-bit, r/w, no-wait. Expansion Bus
 *  nGCS6: 32-bit, r/w, no-wait. SDRAM bank 0
 *  nGCS7: 32-bit, r/w, no-wait. SDRAM bank 1
 */

#define OMAHA_BWSCON_DEF                0x222221A0	 /*  All 32-bit, r/w, no-wait */

/*  Functions:
 *  CS0	- Flash bank 0
 *  CS1	- PLD
 *  CS2	- FPGA
 *  CS3	- FPGA
 *  CS4	- PCMCIA0 (Unused)
 *  CS5	- PCMCIA1 (Unused)
 */
	
/*  CS0 Intel flash devices: 
 */
#define OMAHA_BANKCON0_DEF              0x00007FFC	 /*  Maximum clocks/function */
#define OMAHA_BANKCON1_DEF              0x00007FFC	 /*  Maximum clocks/function */
#define OMAHA_BANKCON2_DEF              0x00007FFC	 /*  Maximum clocks/function */
#define OMAHA_BANKCON3_DEF              0x00002400	 /*  tacs=1, tacc = 6clks */
#define OMAHA_BANKCON4_DEF              0x00007FFC	 /*  Maximum clocks/function */
#define OMAHA_BANKCON5_DEF              0x00007FFC	 /*  Maximum clocks/function */
	  
/*  CS6 SDRAM0 
 */
#define OMAHA_BANKCON6_DEF              0x00018001	 /*  9-bit, 2clks */

/*  CS7 SDRAM1
 */
#define OMAHA_BANKCON7_DEF              0x00018001	 /*  9-bit, 2clks */

/*  refresh (Assumes HCLK = 66MHz)
 *  refresh period = 64msecs (from datasheet) for 8K cycles (8usecs each)
 *  @66MHz busclock, this is 533 cycles...
 */
#define OMAHA_REFRESH_DEF               0x00A405EC	 /*  Refresh enabled, max clk. */

#define OMAHA_BANKSIZE_DEF              0x00000000	 /*  32Mb/32Mb */

/*  mode register	(CL = 3)
 */
#define OMAHA_MRSRB6_DEF                0x00000030
#define OMAHA_MRSRB7_DEF                0x00000030

/* -----------------------------------------------------------------------
 *  CPU Clocking
 * -----------------------------------------------------------------------
 */

/*  There are three important clock domains
 *  FCLK - CPU clock
 *  HCLK - AHB clock
 *  PCLK - APB clock
 */

/*  All clocks are derived from a 12MHz Xtal fed through
 *  PLL's and dividers.
 * 
 *  Note:
 *  HCLK = FCLK / 2
 *  PCLK = HCLK / 2
 * 
 *  Eg. for FCLK = 133MHz, HCLK = 66MHz, PCLK = 33MHz
 */

#define OMAHA_LOCKTIME_DEF              0xFFFFFF	 /*  PLL synchronization time */

/*  Nearest values (Samsung recommended from 12MHz xtal)
 */
#define OMAHA_CLK_33M                   0x25003		 /* ; 33.75 MHz */
#define OMAHA_CLK_66M                   0x25002		 /*   67.50 MHz */
#define OMAHA_CLK_100M                  0x2B011		 /*  102.00 MHz */
#define OMAHA_CLK_133M                  0x51021		 /*  133.50 MHz */

/*  Full speed ahead!
 */
#define OMAHA_CLK_DEFAULT               OMAHA_CLK_133M	

/*  Don't trust the PLL, use SLOW mode (HCLK = 12MHz direct)
 * OMAHA_SLOW		EQU	1
 */

/* -----------------------------------------------------------------------
 *  From PrimeCell UART (PL010) Block Specification (ARM-DDI-0139B)
 * -----------------------------------------------------------------------
 *  UART Base register absolute address
 */
#define OMAHA_UART0_BASE                0x15000000	 /*  Uart 0 base */
#define OMAHA_UART1_BASE                0x15004000	 /*  Uart 1 base */

/*  Offsets into registers of each UART controller
 */
#define OMAHA_ULCON                     0x00		 /*  Line control */
#define OMAHA_UCON                      0x04		 /*  Control */
#define OMAHA_UFCON                     0x08		 /*  FIFO control */
#define OMAHA_UMCON                     0x0C		 /*  Modem control */
#define OMAHA_UTRSTAT                   0x10		 /*  Rx/Tx status */
#define OMAHA_UERSTAT                   0x14		 /*  Rx Error Status */
#define OMAHA_UFSTAT                    0x18		 /*  FIFO status */
#define OMAHA_UMSTAT                    0x1C		 /*  Modem status */
#define OMAHA_UTXH                      0x20		 /*  Transmission Hold (byte wide) */
#define OMAHA_URXH                      0x24		 /*  Receive buffer (byte wide) */
#define OMAHA_UBRDIV                    0x28		 /*  Baud rate divisor */

/*  UART status flags in OMAHA_UTRSTAT
 */
#define OMAHA_URX_FULL                  0x1		 /*  Receive buffer has valid data */
#define OMAHA_UTX_EMPTY                 0x2		 /*  Transmitter has finished */

/* Baud rates supported on the uart. */

#define ARM_BAUD_460800                 460800
#define ARM_BAUD_230400                 230400
#define ARM_BAUD_115200                 115200
#define ARM_BAUD_57600                  57600
#define ARM_BAUD_38400                  38400
#define ARM_BAUD_19200                  19200
#define ARM_BAUD_9600                   9600

/*  LEDs
 *  These are connected to GPIO Port C
 */
#define PLAT_DBG_LEDS                   (PLAT_PERIPHERAL_BASE + OMAHA_PCDAT)	

/* -----------------------------------------------------------------------
 *  Interrupts
 * -----------------------------------------------------------------------
 */

/*  Interrupt numbers
 */
#define OMAHA_INT_EINT0                 0	 /*  FPGA */
#define OMAHA_INT_EINT1                 1	 /*  PLD */
#define OMAHA_INT_EINT2                 2	 /*  Expansion Bus */
#define OMAHA_INT_EINT3                 3	 /*  Ethernet */
#define OMAHA_INT_EINT4                 4	 /*  USB2 */
#define OMAHA_INT_EINT5                 5	 /*  Fan */
#define OMAHA_INT_EINT6                 6	 /*  unused */
#define OMAHA_INT_EINT7                 7	 /*  unused */
#define OMAHA_INT_TICK                  8
#define OMAHA_INT_WDT                   9
#define OMAHA_INT_TIMER0                10
#define OMAHA_INT_TIMER1                11
#define OMAHA_INT_TIMER2                12
#define OMAHA_INT_TIMER3                13
#define OMAHA_INT_TIMER4                14
#define OMAHA_INT_UERR                  15
/*  16 Unused
 */
#define OMAHA_INT_DMA0                  17
#define OMAHA_INT_DMA1                  18
#define OMAHA_INT_DMA2                  19
#define OMAHA_INT_DMA3                  20
#define OMAHA_INT_MMC                   21