platform.h

一个2.4.21版本的嵌入式linux内核

/* DO NOT EDIT!! - this file automatically generated
 *                 from .s file by awk -f s2h.awk
 */
/***********************************************************************
 *    Copyright ARM Limited 1998 - 2001.  All rights reserved.
 * ************************************************************************
 * 
 *   Omaha address map
 * 
 * 	NOTE: This is a multi-hosted header file for use with uHAL and
 * 	      supported debuggers.
 * 
 * 	$Id: platform.h,v 1.12 2002/08/22 15:49:56 ahaigh Exp $
 * 
 *     Everything is defined in terms of PLAT_* and then the key values
 *     are redefined as required for uHAL.
 * 
 *     NOTE: If things are defined in terms of a BASE and lots of OFFSETs,
 * 	the code will be more portable and amenable to being used in
 * 	different (physical vs virtual) memory maps - just change the
 * 	base and the rest will work!
 * 
 * ***********************************************************************/

#ifndef __address_h
#define __address_h                     1

#include "bits.h" 
	
#define PLATFORM_ID                     0x00000800	 /*  TBD */

/*  Common modules for uHAL can be included or excluded by changing these
 *  definitions. These can be over-ridden by the makefile/ARM project file
 *  provided the .h file is rebuilt.
 */

#ifndef USE_C_LIBRARY
#define USE_C_LIBRARY                   0
#endif
#ifndef uHAL_HEAP
#define uHAL_HEAP                       1
#endif
#ifndef uHAL_PCI
#define uHAL_PCI                        0
#endif


/* -----------------------------------------------------------------------
 * 
 *  uHAL always has RAM at 0 and, when a MMU is used, maps everything else
 *  1-1 physical to virtual. 
 */

/* =======================================================================
 *  Omaha
 * =======================================================================
 * -----------------------------------------------------------------------
 *  Memory definitions
 * -----------------------------------------------------------------------
 */

/*  New world memory....
 */

/*  We have eight banks of 32MB, covering the first 256Mb of address space
 */

/*  Bank		Function
 *  0		Flash
 *  1		TBD / ROM
 *  2		TBD / ROM
 *  3		FPGA / sub-chip-selects
 *  4		TBD / ROM
 *  5		TBD / ROM
 *  6		SDRAM Bank 0
 *  7		SDRAM Bank 1
 */


/*  SDRAM	: 64Mbytes. 
 * 
 *  Two banks of 32-bit SDRAM, each 32Mbytes in size.
 *  Bank 0 is on nGCS6, bank 1 is on nGCS7
 */

/*  Physical address
 */
#define PLAT_SDRAM_PHYS0                0x0C000000	 /*  @ 192Mb */
#define PLAT_SDRAM_PHYS1                0x0E000000	 /*  @ 224Mb */

/*  Size of one SDRAM bank
 */
#define PLAT_SDRAM_BANKSIZE             SZ_32M

/*  Virtual address
 */
#define PLAT_SDRAM_BASE                 0x00000000
#define PLAT_SDRAM_SIZE                 SZ_64M

/*  Put page tables in top 1MB of memory; don't let the user access this area.
 */
#define PLAT_PAGETABLE_BASE             0x0FFF0000
#define PLAT_USER_SDRAM_SIZE            PLAT_SDRAM_SIZE - SZ_1M

/*  Flash : 0.5MBytes
 * 
 *  One bank of 8-bit Flash on nGCS0 (SST39VF040-90-4C-NH)
 */

/*  Physical flash device base address
 */
#define PLAT_FLASH_PHYS                 0x00000000	 /*  nCS0 */

/*  Logical address for flash
 */
#define PLAT_FLASH_BASE                 SZ_64M
#define PLAT_FLASH_UNCACHED             SZ_128M
#define PLAT_FLASH_DEVICE_SIZE          SZ_512K		
#define PLAT_FLASH_SIZE                 SZ_512K

/*  Notes
 *  We do not map physical devices at their physical
 *  addresses, because this would overlap the 64Mb of RAM
 *  at the bottom of memory. Instead, they are mostly mapped
 *  at 0x20000000 + Physical address instead
 *  (CPU internal registers live at 0x10000000 + something)
 */

/*  FPGA space (all of nGCS 3)
 */
#define PLAT_FPGA_PHYS                  0x06000000
#define PLAT_FPGA_BASE                  0x26000000
#define PLAT_FPGA_SIZE                  SZ_32M	

/*  PLD live in PLD space in nGCS1
 */
#define PLAT_PLD_PHYS                   0x02800000
#define PLAT_PLD_BASE                   0x22800000
#define PLAT_PLD_SIZE                   SZ_8M

/*  USB2 space
 */
#define PLAT_USB2_PHYS                  0x04000000
#define PLAT_USB2_BASE                  0x24000000
#define PLAT_USB2_SIZE                  0x00200000
			       
/*  Ethernet space
 */
#define PLAT_ETHERNET_PHYS              0x02200000
#define PLAT_ETHERNET_BASE              0x22200000
#define PLAT_ETHERNET_SIZE              0x00200000

/*  TAP Controller space
 */
#define PLAT_TAP_PHYS                   PLAT_FPGA_PHYS
#define PLAT_TAP_BASE                   PLAT_FPGA_BASE
#define PLAT_TAP_SIZE                   SZ_32M

/*  CompactFlash address space (top half on nGCS1)
 */

/*  Notes about the CompactFlash implementation (rev b):
 * 
 *  Since we only need CF ATA cards to work, we
 *  use TrueIDE mode for simplicity.
 * 
 *  However, we need 8-bit access to the Command
 *  Registers, and 16-bit access to the Data-Register.
 *  So we have to access the CF card in two chip select
 *  regions: nCS0 and nCS2.
 * 
 *  In the case of TrueIDE mode, we get the following
 *  (physical) address usage:
 * 
 *  0x01C00000 - 0x01C00007 	- Command Registers (8-bit r/w)
 *  0x01E00006 - 0x01E00006	- Control Register (8-bit r/w)
 *  0x05C00000 - 0x05C00001	- Data Register (16-bit r/w)
 *  
 */

/*  CF 16-bit access in nCS2
 */
#define PLAT_PCMCIA_PHYS                0x05000000
#define PLAT_PCMCIA_BASE                0x25000000
#define PLAT_PCMCIA_SIZE                0x01000000

/*  CF 8-bit access in nCS0
 */
#define PLAT_PCMCIA_8_PHYS              0x01000000
#define PLAT_PCMCIA_8_BASE              0x21000000
#define PLAT_PCMCIA_8_SIZE              0x01000000

/*  Offsets into CF region (applies to both CS regions)
 */
#define PLAT_PCMCIA_ATTR                0x00800000
#define PLAT_PCMCIA_MEM                 0x00A00000
#define PLAT_PCMCIA_IO                  0x00C00000	 /*  CE1 in TrueIDE */
#define PLAT_PCMCIA_IO_ALT              0x00E00000	 /*  CE2 in TrueIDE */

/*  Expansion Bus memory region (nGCS4 and nGCS5)
 */
#define PLAT_BUS_PHYS                   0x08000000
#define PLAT_BUS_BASE                   0x28000000
#define PLAT_BUS_SIZE                   0x04000000

/*  Location of high vectors used by operating system
 *  If we may this, then we can seamlessly debug
 *  from a uHAL program into an OS using high-vectors,
 *  since we are always going to need exception handlers,
 *  and they can only be in two places (0x0 and 0xFFFF0000)!
 */
#define PLAT_HIVECS_PHYS                0xFFFF0000
#define PLAT_HIVECS_BASE                0xFFFF0000
#define PLAT_HIVECS_SIZE                SZ_1M

/*  Remaining chip-select regions
 *  Leave these un-mapped for the moment
 */


/*  ----------------------------------------------------------------------
 *  S3C2400X01 CPU peripherals
 * -----------------------------------------------------------------------
 */

/*  AHB peripherals appear in the lower 16Mb, APB in the upper 16Mb
 */

/*  All peripherals are offsets from PLAT_PERIPHERAL_BASE
 */

#define PLAT_PERIPHERAL_BASE            0x14000000
#define PLAT_PERIPHERAL_SIZE            SZ_32M

/*  Memory Controller
 */
#define OMAHA_BWSCON                    0x00	 /*  Bus width and wait state control */
#define OMAHA_BANKCON0                  0x04	 /*  Boot ROM control (Bank 0) */
#define OMAHA_BANKCON1                  0x08	 /*  Bank 1 control */
#define OMAHA_BANKCON2                  0x0C	 /*  Bank 2 control */
#define OMAHA_BANKCON3                  0x10	 /*  Bank 3 control */
#define OMAHA_BANKCON4                  0x14	 /*  Bank 4 control */
#define OMAHA_BANKCON5                  0x18	 /*  Bank 5 control */
#define OMAHA_BANKCON6                  0x1C	 /*  Bank 6 control */
#define OMAHA_BANKCON7                  0x20	 /*  Bank 7 control */

#define OMAHA_REFRESH                   0x24	 /*  SDRAM refresh control */
#define OMAHA_BANKSIZE                  0x28	 /*  Flexible bank size */
#define OMAHA_MRSRB6                    0x2C	 /*  Mode register set for SDRAM Bank 0 (nGCS6) */
#define OMAHA_MRSRB7                    0x30	 /*  Mode register set for SDRAM Bank 1 (nGCS7) */

/*  Interrupt controller
 */
#define OMAHA_SRCPND                    0x400000	 /*  Interrupt sources pending */
#define OMAHA_INTMOD                    0x400004	 /*  Interrupt mode control */
#define OMAHA_INTMSK                    0x400008	 /*  Interrupt mask control */
#define OMAHA_PRIORITY                  0x40000C	 /*  Int. priority control */
#define OMAHA_INTPND                    0x400010	 /*  Interrupts pending */
#define OMAHA_INTOFFSET                 0x400014	 /*  IRQ source */

/*  Clock / Power management
 */
#define OMAHA_LOCKTIME                  0x800000	 /*  PLL Lock time counter */
#define OMAHA_MPLLCON                   0x800004	 /*  MPLL Control */
#define OMAHA_UPLLCON                   0x800008	 /*  UPLL Control */
#define OMAHA_CLKCON                    0x80000C	 /*  Clock control */
#define OMAHA_CLKSLOW                   0x800010	 /*  Slow clock control */
#define OMAHA_CLKDIVN                   0x800014	 /*  Clock divider control */

/*  LCD Control
 */

/*  UARTs
 */
#define OMAHA_ULCON0                    0x1000000	 /*  UART 0 Line control */
#define OMAHA_ULCON1                    0x1004000	 /*  UART 1 Line control */