📄 regmap.h
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#define ECLINE5 (SECURITY_BASE+0x2824)#define ECLINE6 (SECURITY_BASE+0x2828)#define ECLINE7 (SECURITY_BASE+0x282C)#define ETWIDX1 (SECURITY_BASE+0x2840)#define ETWL1 (SECURITY_BASE+0x2844)#define ETWIDX2 (SECURITY_BASE+0x2848)#define ETWL2 (SECURITY_BASE+0x284C)#define ETSPT10 (SECURITY_BASE+0x4000)#define ETSPT11 (SECURITY_BASE+0x4004)#define ETSPT12 (SECURITY_BASE+0x4008)#define ETSPT13 (SECURITY_BASE+0x400C)#define ETSPT2000 (SECURITY_BASE+0x6000)#define ETSPT2020 (SECURITY_BASE+0x6020)#define ETSPT2024 (SECURITY_BASE+0x6024)/* 8084_0000 - 8084_ffff: GPIO */#define GPIO_OFFSET 0x040000#define GPIO_BASE (EP93XX_APB_BASE|GPIO_OFFSET)#define GPIO_PADR (GPIO_BASE+0x00)#define GPIO_PBDR (GPIO_BASE+0x04)#define GPIO_PCDR (GPIO_BASE+0x08)#define GPIO_PDDR (GPIO_BASE+0x0C)#define GPIO_PADDR (GPIO_BASE+0x10)#define GPIO_PBDDR (GPIO_BASE+0x14)#define GPIO_PCDDR (GPIO_BASE+0x18)#define GPIO_PDDDR (GPIO_BASE+0x1C)#define GPIO_PEDR (GPIO_BASE+0x20)#define GPIO_PEDDR (GPIO_BASE+0x24)// #define 0x8084.0028 Reserved// #define 0x8084.002C Reserved#define GPIO_PFDR (GPIO_BASE+0x30) #define GPIO_PFDDR (GPIO_BASE+0x34)#define GPIO_PGDR (GPIO_BASE+0x38)#define GPIO_PGDDR (GPIO_BASE+0x3C)#define GPIO_PHDR (GPIO_BASE+0x40)#define GPIO_PHDDR (GPIO_BASE+0x44)// #define 0x8084.0048 RAZ RAZ #define GPIO_FINTTYPE1 (GPIO_BASE+0x4C)#define GPIO_FINTTYPE2 (GPIO_BASE+0x50)#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */#define GPIO_FINTEN (GPIO_BASE+0x58)#define GPIO_INTSTATUSF (GPIO_BASE+0x5C)#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60) #define GPIO_FDB (GPIO_BASE+0x64)#define GPIO_PAPINDR (GPIO_BASE+0x68)#define GPIO_PBPINDR (GPIO_BASE+0x6C)#define GPIO_PCPINDR (GPIO_BASE+0x70)#define GPIO_PDPINDR (GPIO_BASE+0x74)#define GPIO_PEPINDR (GPIO_BASE+0x78)#define GPIO_PFPINDR (GPIO_BASE+0x7C)#define GPIO_PGPINDR (GPIO_BASE+0x80)#define GPIO_PHPINDR (GPIO_BASE+0x84)#define GPIO_AINTTYPE1 (GPIO_BASE+0x90)#define GPIO_AINTTYPE2 (GPIO_BASE+0x94)#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */#define GPIO_AINTEN (GPIO_BASE+0x9C)#define GPIO_INTSTATUSA (GPIO_BASE+0xA0)#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4)#define GPIO_ADB (GPIO_BASE+0xA8)#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC)#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0)#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */#define GPIO_BINTEN (GPIO_BASE+0xB8)#define GPIO_INTSTATUSB (GPIO_BASE+0xBC)#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0)#define GPIO_BDB (GPIO_BASE+0xC4)#define GPIO_EEDRIVE (GPIO_BASE+0xC8)//#define Reserved (GPIO_BASE+0xCC)#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers *//* 8085_0000 - 8085_ffff: Reserved *//* 8086_0000 - 8086_ffff: Reserved *//* 8087_0000 - 8087_ffff: Reserved *//* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */#define AC97_OFFSET 0x080000#define AC97_BASE (EP93XX_APB_BASE|AC97_OFFSET)#define AC97DR1 (AC97_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */#define AC97RXCR1 (AC97_BASE+0x04) /* 8088.0004 R/W Control register for receive */#define AC97TXCR1 (AC97_BASE+0x08) /* 8088.0008 R/W Control register for transmit */#define AC97SR1 (AC97_BASE+0x0C) /* 8088.000C R Status register */#define AC97RISR1 (AC97_BASE+0x10) /* 8088.0010 R Raw interrupt status register */#define AC97ISR1 (AC97_BASE+0x14) /* 8088.0014 R Interrupt Status */#define AC97IE1 (AC97_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */ /* 8088.001C Reserved - RAZ */#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ /* 8088.003C Reserved - RAZ */#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ /* 8088.005C Reserved - RAZ */#define AC97DR4 (AC97_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */#define AC97RXCR4 (AC97_BASE+0x64) /* 8088.0064 R/W Control register for receive */#define AC97TXCR4 (AC97_BASE+0x68) /* 8088.0068 R/W Control register for transmit */#define AC97SR4 (AC97_BASE+0x6C) /* 8088.006C R Status register */#define AC97RISR4 (AC97_BASE+0x70) /* 8088.0070 R Raw interrupt status register */#define AC97ISR4 (AC97_BASE+0x74) /* 8088.0074 R Interrupt Status */#define AC97IE4 (AC97_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */ /* 8088.007C Reserved - RAZ */#define AC97S1DATA (AC97_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */#define AC97S2DATA (AC97_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */#define AC97S12DATA (AC97_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */#define AC97RGIS (AC97_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register*/#define AC97GIS (AC97_BASE+0x90) /* 8088.0090 R Global interrupt status register */#define AC97IM (AC97_BASE+0x94) /* 8088.0094 R/W Interrupt mask register */#define AC97EOI (AC97_BASE+0x98) /* 8088.0098 W Interrupt clear register */#define AC97GCR (AC97_BASE+0x9C) /* 8088.009C R/W Main Control register */#define AC97RESET (AC97_BASE+0xA0) /* 8088.00A0 R/W RESET control register. */#define AC97SYNC (AC97_BASE+0xA4) /* 8088.00A4 R/W SYNC control register. */#define AC97GCIS (AC97_BASE+0xA8) /* 8088.00A8 R Global chan FIFO int status register *//* 8089_0000 - 8089_ffff: Reserved *//* 808A_0000 - 808A_ffff: SSP - (SPI) */#define SSP_OFFSET 0x0A0000#define SSP_BASE (EP93XX_APB_BASE|SSP_OFFSET)#define SSPCR0 (SSP_BASE+0x00)#define SSPCR1 (SSP_BASE+0x04)#define SSPDR (SSP_BASE+0x08)#define SSPSR (SSP_BASE+0x0c)#define SSPCPSR (SSP_BASE+0x10)#define SSPIIR (SSP_BASE+0x14)/*808B_0000 - 808B_ffff: IrDA */#define IRDA_OFFSET 0x0B0000#define IRDA_BASE (EP93XX_APB_BASE|IRDA_OFFSET)#define IrEnable (IRDA_BASE+0x00)#define IrCtrl (IRDA_BASE+0x04)#define IrAdrMatchVal (IRDA_BASE+0x08)#define IrFlag (IRDA_BASE+0x0C)#define IrData (IRDA_BASE+0x10)#define IrDataTail1 (IRDA_BASE+0x14)#define IrDataTail2 (IRDA_BASE+0x18)#define IrDataTail3 (IRDA_BASE+0x1c)#define IrRIB (IRDA_BASE+0x20)#define IrTR0 (IRDA_BASE+0x24)#define IrDMACR (IRDA_BASE+0x28)#define SIRTR0 (IRDA_BASE+0x30)#define MISR (IRDA_BASE+0x80)#define MIMR (IRDA_BASE+0x84)#define MIIR (IRDA_BASE+0x88)#define FISR (IRDA_BASE+0x180)#define FIMR (IRDA_BASE+0x184)#define FIIR (IRDA_BASE+0x188)/* 808C_0000 - 808C_ffff: UART1 */#define UART1_OFFSET 0x0C0000#define UART1_BASE (EP93XX_APB_BASE|UART1_OFFSET)#define UART1DR (UART1_BASE+0x000)#define UART1RSR (UART1_BASE+0x004)#define UART1ECR (UART1_BASE+0x004)#define UART1CR_H (UART1_BASE+0x008)#define UART1CR_M (UART1_BASE+0x00C)#define UART1CR_L (UART1_BASE+0x010)#define UART1CR (UART1_BASE+0x014)#define UART1FR (UART1_BASE+0x018)#define UART1IIR (UART1_BASE+0x01C)#define UART1ICR (UART1_BASE+0x01C)#define UART1ILPR (UART1_BASE+0x020)#define UART1DMACR (UART1_BASE+0x028)#define UART1TMR (UART1_BASE+0x084)#define UART1MCR (UART1_BASE+0x100)#define UART1MSR (UART1_BASE+0x104)#define UART1TCR (UART1_BASE+0x108)#define UART1TISR (UART1_BASE+0x10C)#define UART1TOCR (UART1_BASE+0x110)#define HDLC1CR (UART1_BASE+0x20c)#define HDLC1AMV (UART1_BASE+0x210)#define HDLC1AMSK (UART1_BASE+0x214)#define HDLC1RIB (UART1_BASE+0x218)#define HDLC1SR (UART1_BASE+0x21c)/* 808d_0000 - 808d_ffff: UART2 */#define UART2_OFFSET 0x0D0000#define UART2_BASE (EP93XX_APB_BASE|UART2_OFFSET)#define UART2DR (UART2_BASE+0x00)#define UART2RSR (UART2_BASE+0x04) /* Read */#define UART2ECR (UART2_BASE+0x04) /* Write */#define UART2CR_H (UART2_BASE+0x08)#define UART2CR_M (UART2_BASE+0x0C)#define UART2CR_L (UART2_BASE+0x10)#define UART2CR (UART2_BASE+0x14)#define UART2FR (UART2_BASE+0x18)#define UART2IIR (UART2_BASE+0x1C) /* Read */#define UART2ICR (UART2_BASE+0x1C) /* Write */#define UART2ILPR (UART2_BASE+0x20)#define UART2DMACR (UART2_BASE+0x28)#define UART2TMR (UART2_BASE+0x84)/* 808e_0000 - 808e_ffff: UART3 */#define UART3_OFFSET 0x0E0000#⌨️ 快捷键说明
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