regmap.h

一个2.4.21版本的嵌入式linux内核

/*
 *  File:   linux/include/asm-arm/arch-ep93xx/regmap.h
 *
 *  Copyright (C) 2003 Cirrus Logic, Inc
 *  
 *  Copyright (C) 1999 ARM Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <asm/sizes.h> 

#ifndef __ASM_ARCH_REGMAP_H
#define __ASM_ARCH_REGMAP_H

/*
 * Where in virtual memory the IO devices (timers, system controllers
 * and so on).  This gets used in arch/arm/mach-ep93xx/mm.c.
 */
#define IO_BASE_VIRT        0xFF000000     // Virtual address of IO 
#define IO_BASE_PHYS        0x80000000     // Physical address of IO
#define IO_SIZE             0x00A00000     // How much?

/*
 * We don't map the PCMCIA initially.  The PCMCIA driver will use ioremap
 * to be able to see it.  But besides that PCMCIA will not exist in the
 * memory map.
 */
#define PCMCIA_BASE_VIRT    0xD0000000     // Virtual address of PCMCIA
#define PCMCIA_BASE_PHYS    0x40000000     // Physical address of PCMCIA
#define PCMCIA_SIZE         0x10000000     // How much?

/*
 * The memory maps and register lists below show physical addresses, while the
 * corresponding #defines use virtual addresses.
 */

/******************************************************************/
/*         EP93xx Memory Map and Register list                    */
/******************************************************************/
/*                                                                */
/* 0000_0000 - 0000_03ff: Internal ROM Memory  (Remap Low)        */
/* 0000_0400 - 1fff_ffff: External DRAM Memory (Remap Low)        */
/* 0000_0000 - 1fff_ffff: External DRAM Memory (Remap High)       */
/* 2000_0000 - 7fff_ffff: External SRAM Memory                    */
/* 8800_0000 - 8fff_ffff: Expansion Device Memory and Registers   */
/* 9000_0000 - 9fff_ffff: Expansion memory                        */
/* A000_0000 - Afff_ffff: PCMCIA Memory, I/O, and Attribute space */
/* B000_0000 - ffff_ffff: External SRAM memory                    */

/******************************************************************/
/*           EP93xx AHB Blocks Base Address                       */
/******************************************************************/
/*                                                                */
/* The AHB device address map is:                                 */
/* Start     End        Size Usage                                */
/* 8000_0000 8000_FFFF: 64 K DMA control registers                */
/* 8001_0000 8001_FFFF: 64 K Ethernet MAC control registers       */
/* 8002_0000 8002_FFFF: 64 K USB Host control registers           */
/* 8003_0000 8003_FFFF: 64 K Raster control registers             */
/* 8004_0000 8004_FFFF: 64 K Graphics control registers           */
/* 8005_0000 8005_FFFF: 64 K Reserved                             */
/* 8006_0000 8006_FFFF: 64 K SDRAM control registes               */
/* 8007_0000 8007_FFFF: 64 K ARM920T slave                        */
/* 8008_0000 8008_FFFF: 64 K SMC_PCMCIA control registers         */
/* 8009_0000 8009_FFFF: 64 K Boot ROM physical address            */
/* 800A_0000 800A_FFFF: 64 K IDE control registers                */
/* 800B_0000 800B_FFFF: 64 K VIC1 control registers               */
/* 800C_0000 800C_FFFF: 64 K VIC2 control registers               */
/* TAG: literal */
#define EP93XX_AHB_BASE (IO_BASE_VIRT)

/* ARM920T Address Description                             */
/*                                                         */
/* 0x8000.0000 -> 0x8000.003C M2P Channel 0 Registers (Tx) */
/* 0x8000.0040 -> 0x8000.007C M2P Channel 1 Registers (Rx) */
/* 0x8000.0080 -> 0x8000.00BC M2P Channel 2 Registers (Tx) */ 
/* 0x8000.00C0 -> 0x8000.00FC M2P Channel 3 Registers (Rx) */
/* 0x8000.0100 -> 0x8000.013C M2M Channel 0 Registers      */
/* 0x8000.0140 -> 0x8000.017C M2M Channel 1 Registers      */
/* 0x8000.0180 -> 0x8000.01BC Not Used                     */
/* 0x8000.01C0 -> 0x8000.01FC Not Used                     */
/* 0x8000.0200 -> 0x8000.023C M2P Channel 5 Registers (Rx) */
/* 0x8000.0240 -> 0x8000.027C M2P Channel 4 Registers (Tx) */
/* 0x8000.0280 -> 0x8000.02BC M2P Channel 7 Registers (Rx) */
/* 0x8000.02C0 -> 0x8000.02FC M2P Channel 6 Registers (Tx) */
/* 0x8000.0300 -> 0x8000.033C M2P Channel 9 Registers (Rx) */
/* 0x8000.0340 -> 0x8000.037C M2P Channel 8 Registers (Tx) */
/* 0x8000.0380 DMA Channel Arbitration register            */
/* 0x8000.03C0 DMA Global Interrupt register               */
/* 0x8000.03C4 -> 0x8000.03FC Not Used                     */


/* Internal M2P/P2M Channel Register Map                   */

/* Offset Name      Access  Bits Reset Value               */
/* 0x00   CONTROL   R/W     6    0                         */
/* 0x04   INTERRUPT R/W TC* 3    0                         */
/* 0x08   PPALLOC   R/W     4    channel dependant         */
/*                               (see reg description)     */
/* 0x0C   STATUS    RO      8    0                         */
/* 0x10   reserved                                         */
/* 0x14   REMAIN    RO      16   0                         */
/* 0X18   Reserved                                         */
/* 0X1C   Reserved                                         */
/* 0x20   MAXCNT0   R/W     16   0                         */
/* 0x24   BASE0     R/W     32   0                         */
/* 0x28   CURRENT0  RO      32   0                         */
/* 0x2C   Reserved                                         */
/* 0x30   MAXCNT1   R/W     16   0                         */
/* 0x34   BASE1     R/W     32   0                         */
/* 0X38   CURRENT1  RO      32   0                         */
/* 0X3C   Reserved                                         */
/*                                                         */
/* M2M Channel Register Map                                */
/* Offset Name         Access   Bits Reset Value           */
/*                                                         */
/* 0x00   CONTROL      R/W      22   0                     */
/* 0x04   INTERRUPT    R/W TC*  3    0                     */
/* 0x08   Reserved                                         */
/* 0x0C   STATUS       R/W TC*  14   0                     */
/* 0x10   BCR0         R/W      16   0                     */
/* 0x14   BCR1         R/W      16   0                     */
/* 0x18   SAR_BASE0    R/W      32   0                     */
/* 0x1C   SAR_BASE1    R/W      32   0                     */
/* 0x20   Reserved                                         */
/* 0x24   SAR_CURRENT0 RO       32   0                     */
/* 0x28   SAR_CURRENT1 RO       32   0                     */
/* 0x2C   DAR_BASE0    R/W      32   0                     */
/* 0x30   DAR_BASE1    R/W      32   0                     */
/* 0x34   DAR_CURRENT0 RO       32   0                     */
/* 0X38   Reserved                                         */
/* 0X3C   DAR_CURRENT1 RO       32   0                     */     
/* * Write this location once to clear the bit (see        */
/* Interrupt/Status register description for which bits    */
/* this rule applies to).                                  */

/* 8000_0000 - 8000_ffff: DMA  */
#define DMA_OFFSET              0x000000
#define DMA_BASE                (EP93XX_AHB_BASE|DMA_OFFSET)
#define DMAMP_TX_0_CONTROL      (DMA_BASE+0x0000)
#define DMAMP_TX_0_INTERRUPT    (DMA_BASE+0x0004)
#define DMAMP_TX_0_PPALLOC      (DMA_BASE+0x0008)
#define DMAMP_TX_0_STATUS       (DMA_BASE+0x000C)       
#define DMAMP_TX_0_REMAIN       (DMA_BASE+0x0014)
#define DMAMP_TX_0_MAXCNT0      (DMA_BASE+0x0020)
#define DMAMP_TX_0_BASE0        (DMA_BASE+0x0024)
#define DMAMP_TX_0_CURRENT0     (DMA_BASE+0x0028)
#define DMAMP_TX_0_MAXCNT1      (DMA_BASE+0x0030)
#define DMAMP_TX_0_BASE1        (DMA_BASE+0x0034)
#define DMAMP_TX_0_CURRENT1     (DMA_BASE+0x0038)

#define DMAMP_RX_1_CONTROL      (DMA_BASE+0x0040)
#define DMAMP_RX_1_INTERRUPT    (DMA_BASE+0x0044)
#define DMAMP_RX_1_PPALLOC      (DMA_BASE+0x0048)
#define DMAMP_RX_1_STATUS       (DMA_BASE+0x004C)       
#define DMAMP_RX_1_REMAIN       (DMA_BASE+0x0054)
#define DMAMP_RX_1_MAXCNT0      (DMA_BASE+0x0060)
#define DMAMP_RX_1_BASE0        (DMA_BASE+0x0064)
#define DMAMP_RX_1_CURRENT0     (DMA_BASE+0x0068)
#define DMAMP_RX_1_MAXCNT1      (DMA_BASE+0x0070)
#define DMAMP_RX_1_BASE1        (DMA_BASE+0x0074)
#define DMAMP_RX_1_CURRENT1     (DMA_BASE+0x0078)

#define DMAMP_TX_2_CONTROL      (DMA_BASE+0x0080)
#define DMAMP_TX_2_INTERRUPT    (DMA_BASE+0x0084)
#define DMAMP_TX_2_PPALLOC      (DMA_BASE+0x0088)
#define DMAMP_TX_2_STATUS       (DMA_BASE+0x008C)       
#define DMAMP_TX_2_REMAIN       (DMA_BASE+0x0094)
#define DMAMP_TX_2_MAXCNT0      (DMA_BASE+0x00A0)
#define DMAMP_TX_2_BASE0        (DMA_BASE+0x00A4)
#define DMAMP_TX_2_CURRENT0     (DMA_BASE+0x00A8)
#define DMAMP_TX_2_MAXCNT1      (DMA_BASE+0x00B0)
#define DMAMP_TX_2_BASE1        (DMA_BASE+0x00B4)
#define DMAMP_TX_2_CURRENT1     (DMA_BASE+0x00B8)

#define DMAMP_RX_3_CONTROL      (DMA_BASE+0x00C0)
#define DMAMP_RX_3_INTERRUPT    (DMA_BASE+0x00C4)
#define DMAMP_RX_3_PPALLOC      (DMA_BASE+0x00C8)
#define DMAMP_RX_3_STATUS       (DMA_BASE+0x00CC)       
#define DMAMP_RX_3_REMAIN       (DMA_BASE+0x00D4)
#define DMAMP_RX_3_MAXCNT0      (DMA_BASE+0x00E0)
#define DMAMP_RX_3_BASE0        (DMA_BASE+0x00E4)
#define DMAMP_RX_3_CURRENT0     (DMA_BASE+0x00E8)
#define DMAMP_RX_3_MAXCNT1      (DMA_BASE+0x00F0)
#define DMAMP_RX_3_BASE1        (DMA_BASE+0x00F4)
#define DMAMP_RX_3_CURRENT1     (DMA_BASE+0x00F8)

#define DMAMM_0_CONTROL         (DMA_BASE+0x0100)
#define DMAMM_0_INTERRUPT       (DMA_BASE+0x0104)
#define DMAMM_0_STATUS          (DMA_BASE+0x010C)
#define DMAMM_0_BCR0            (DMA_BASE+0x0110)
#define DMAMM_0_BCR1            (DMA_BASE+0x0114)
#define DMAMM_0_SAR_BASE0       (DMA_BASE+0x0118)
#define DMAMM_0_SAR_BASE1       (DMA_BASE+0x011C)
#define DMAMM_0_SAR_CURRENT0    (DMA_BASE+0x0124)
#define DMAMM_0_SAR_CURRENT1    (DMA_BASE+0x0128)
#define DMAMM_0_DAR_BASE0       (DMA_BASE+0x012C)
#define DMAMM_0_DAR_BASE1       (DMA_BASE+0x0130)
#define DMAMM_0_DAR_CURRENT0    (DMA_BASE+0x0134)
#define DMAMM_0_DAR_CURRENT1    (DMA_BASE+0x013C)

#define DMAMM_1_CONTROL         (DMA_BASE+0x0140)
#define DMAMM_1_INTERRUPT       (DMA_BASE+0x0144)
#define DMAMM_1_STATUS          (DMA_BASE+0x014C)
#define DMAMM_1_BCR0            (DMA_BASE+0x0150)       
#define DMAMM_1_BCR1            (DMA_BASE+0x0154)
#define DMAMM_1_SAR_BASE0       (DMA_BASE+0x0158)
#define DMAMM_1_SAR_BASE1       (DMA_BASE+0x015C)
#define DMAMM_1_SAR_CURRENT0    (DMA_BASE+0x0164)
#define DMAMM_1_SAR_CURRENT1    (DMA_BASE+0x0168)
#define DMAMM_1_DAR_BASE0       (DMA_BASE+0x016C)
#define DMAMM_1_DAR_BASE1       (DMA_BASE+0x0170)
#define DMAMM_1_DAR_CURRENT0    (DMA_BASE+0x0174)
#define DMAMM_1_DAR_CURRENT1    (DMA_BASE+0x017C)

#define DMAMP_RX_5_CONTROL      (DMA_BASE+0x0200)
#define DMAMP_RX_5_INTERRUPT    (DMA_BASE+0x0204)
#define DMAMP_RX_5_PPALLOC      (DMA_BASE+0x0208)
#define DMAMP_RX_5_STATUS       (DMA_BASE+0x020C)       
#define DMAMP_RX_5_REMAIN       (DMA_BASE+0x0214)