📄 bridge.h

📁 一个2.4.21版本的嵌入式linux内核
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 * Buffer (x) Flush Count w/o Data Touch Register * * This counter is incremented each time the corresponding response buffer * is flushed without any data element in the buffer being used. A word * write to this address clears the count. */#define BRIDGE_BUF_0_FLUSH_NOTOUCH  0x00040c#define BRIDGE_BUF_2_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1)#define BRIDGE_BUF_4_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2)#define BRIDGE_BUF_6_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3)#define BRIDGE_BUF_8_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4)#define BRIDGE_BUF_10_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5)#define BRIDGE_BUF_12_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6)#define BRIDGE_BUF_14_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7)/* * Buffer (x) Request in Flight Count Register * * This counter is incremented on each bus clock while the request is in * flight. A word write to this address clears the count. */#define BRIDGE_BUF_0_INFLIGHT	 0x000414#define BRIDGE_BUF_2_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1)#define BRIDGE_BUF_4_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2)#define BRIDGE_BUF_6_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3)#define BRIDGE_BUF_8_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4)#define BRIDGE_BUF_10_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5)#define BRIDGE_BUF_12_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6)#define BRIDGE_BUF_14_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7)/* * Buffer (x) Prefetch Request Count Register * * This counter is incremented each time the request using this buffer was * generated from the prefetcher. A word write to this address clears the * count. */#define BRIDGE_BUF_0_PREFETCH	 0x00041C#define BRIDGE_BUF_2_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1)#define BRIDGE_BUF_4_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2)#define BRIDGE_BUF_6_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3)#define BRIDGE_BUF_8_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4)#define BRIDGE_BUF_10_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5)#define BRIDGE_BUF_12_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6)#define BRIDGE_BUF_14_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7)/* * Buffer (x) Total PCI Retry Count Register * * This counter is incremented each time a PCI bus retry occurs and the ad * dress matches the tag for the selected buffer. The buffer must also has * this request in-flight. A word write to this address clears the count. */#define BRIDGE_BUF_0_PCI_RETRY	 0x000424#define BRIDGE_BUF_2_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1)#define BRIDGE_BUF_4_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2)#define BRIDGE_BUF_6_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3)#define BRIDGE_BUF_8_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4)#define BRIDGE_BUF_10_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5)#define BRIDGE_BUF_12_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6)#define BRIDGE_BUF_14_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7)/* * Buffer (x) Max PCI Retry Count Register * * This counter is contains the maximum retry count for a single request * which was in-flight for this buffer. A word write to this address * clears the count. */#define BRIDGE_BUF_0_MAX_PCI_RETRY	 0x00042C#define BRIDGE_BUF_2_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1)#define BRIDGE_BUF_4_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2)#define BRIDGE_BUF_6_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3)#define BRIDGE_BUF_8_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4)#define BRIDGE_BUF_10_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5)#define BRIDGE_BUF_12_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6)#define BRIDGE_BUF_14_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7)/* * Buffer (x) Max Latency Count Register * * This counter is contains the maximum count (in bus clocks) for a single * request which was in-flight for this buffer. A word write to this * address clears the count. */#define BRIDGE_BUF_0_MAX_LATENCY	 0x000434#define BRIDGE_BUF_2_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1)#define BRIDGE_BUF_4_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2)#define BRIDGE_BUF_6_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3)#define BRIDGE_BUF_8_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4)#define BRIDGE_BUF_10_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5)#define BRIDGE_BUF_12_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6)#define BRIDGE_BUF_14_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7)/* * Buffer (x) Clear All Register * * Any access to this register clears all the count values for the (x) * registers. */#define BRIDGE_BUF_0_CLEAR_ALL	 0x00043C#define BRIDGE_BUF_2_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1)#define BRIDGE_BUF_4_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2)#define BRIDGE_BUF_6_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3)#define BRIDGE_BUF_8_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4)#define BRIDGE_BUF_10_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5)#define BRIDGE_BUF_12_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6)#define BRIDGE_BUF_14_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7)/* end of Performance Monitor Registers *//* Byte offset macros for Bridge I/O space. * * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx * macros (below) as they will handle [X]Bridge and PIC. For example, * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0 */#define BRIDGE_ATE_RAM		0x00010000	/* Internal Addr Xlat Ram */#define BRIDGE_TYPE0_CFG_DEV0	0x00020000	/* Type 0 Cfg, Device 0 */#define BRIDGE_TYPE0_CFG_SLOT_OFF	0x00001000	/* Type 0 Cfg Slot Offset (1..7) */#define BRIDGE_TYPE0_CFG_FUNC_OFF	0x00000100	/* Type 0 Cfg Func Offset (1..7) */#define BRIDGE_TYPE0_CFG_DEV(s)		(BRIDGE_TYPE0_CFG_DEV0+\					 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)#define BRIDGE_TYPE0_CFG_DEVF(s,f)	(BRIDGE_TYPE0_CFG_DEV0+\					 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\					 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)#define BRIDGE_TYPE1_CFG	0x00028000	/* Type 1 Cfg space */#define BRIDGE_PCI_IACK		0x00030000	/* PCI Interrupt Ack */#define BRIDGE_EXT_SSRAM	0x00080000	/* Extern SSRAM (ATE) *//* Byte offset macros for Bridge device IO spaces */#define BRIDGE_DEV_CNT		8	/* Up to 8 devices per bridge */#define BRIDGE_DEVIO0		0x00200000	/* Device IO 0 Addr */#define BRIDGE_DEVIO1		0x00400000	/* Device IO 1 Addr */#define BRIDGE_DEVIO2		0x00600000	/* Device IO 2 Addr */#define BRIDGE_DEVIO_OFF	0x00100000	/* Device IO Offset (3..7) */#define BRIDGE_DEVIO_2MB	0x00200000	/* Device IO Offset (0..1) */#define BRIDGE_DEVIO_1MB	0x00100000	/* Device IO Offset (2..7) */#ifndef __ASSEMBLY__#define BRIDGE_DEVIO(x)		((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)/* * The device space macros for PIC are more complicated because the PIC has * two PCI/X bridges under the same widget.  For PIC bus 0, the addresses are * basically the same as for the [X]Bridge.  For PIC bus 1, the addresses are * offset by 0x800000.   Here are two sets of macros.  They are  * "PCIBRIDGE_xxx" that return the address based on the supplied bus number * and also equivalent "PCIBR_xxx" macros that may be used with a * pcibr_soft_s structure.   Both should work with all bridges. */#define PIC_BUS1_OFFSET 0x800000#define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \    ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \                    BRIDGE_TYPE0_CFG_DEV0)#define PCIBRIDGE_TYPE1_CFG(busnum) \    ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG)#define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \        (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\        (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)#define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \        (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\        (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\        (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)#define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \        (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0)#define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \        (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1)#define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \        (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2)#define PCIBRIDGE_DEVIO(busnum, x) \    ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \        PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB)#define PCIBR_BRIDGE_DEVIO0(ps)     PCIBRIDGE_DEVIO0((ps)->bs_busnum)#define PCIBR_BRIDGE_DEVIO1(ps)     PCIBRIDGE_DEVIO1((ps)->bs_busnum)#define PCIBR_BRIDGE_DEVIO2(ps)     PCIBRIDGE_DEVIO2((ps)->bs_busnum)#define PCIBR_BRIDGE_DEVIO(ps, s)   PCIBRIDGE_DEVIO((ps)->bs_busnum, s)#define PCIBR_TYPE1_CFG(ps)         PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum)#define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0)#define PCIBR_TYPE0_CFG_DEV(ps, s) \    ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) : \		  	     PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s))#define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) \    ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) : \			     PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,s,f))#endif				/* LANGUAGE_C */#define BRIDGE_EXTERNAL_FLASH	0x00C00000	/* External Flash PROMS *//* ======================================================================== *    Bridge register bit field definitions *//* Widget part number of bridge */#define BRIDGE_WIDGET_PART_NUM		0xc002#define XBRIDGE_WIDGET_PART_NUM		0xd002/* Manufacturer of bridge */#define BRIDGE_WIDGET_MFGR_NUM		0x036#define XBRIDGE_WIDGET_MFGR_NUM		0x024/* Revision numbers for known [X]Bridge revisions */#define BRIDGE_REV_A			0x1#define BRIDGE_REV_B			0x2#define BRIDGE_REV_C			0x3#define	BRIDGE_REV_D			0x4#define XBRIDGE_REV_A			0x1#define XBRIDGE_REV_B			0x2/* macros to determine bridge type. 'wid' == widget identification */#define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \			XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM)#define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \			XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM)#define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \			XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)#define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \			XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)#define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid))/* Part + Rev numbers allows distinction and acscending sequence */#define BRIDGE_PART_REV_A	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A)#define BRIDGE_PART_REV_B	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B)#define BRIDGE_PART_REV_C	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C)#define	BRIDGE_PART_REV_D	(BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D)#define XBRIDGE_PART_REV_A	(XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A)#define XBRIDGE_PART_REV_B	(XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B)/* Bridge widget status register bits definition */#define PIC_STAT_PCIX_SPEED             (0x3ull << 34)#define PIC_STAT_PCIX_ACTIVE            (0x1ull << 33)#define BRIDGE_STAT_LLP_REC_CNT		(0xFFu << 24)#define BRIDGE_STAT_LLP_TX_CNT		(0xFF << 16)#define BRIDGE_STAT_FLASH_SELECT	(0x1 << 6)#define BRIDGE_STAT_PCI_GIO_N		(0x1 << 5)#define BRIDGE_STAT_PENDING		(0x1F << 0)/* Bridge widget control register bits definition */#define PIC_CTRL_NO_SNOOP		(0x1ull << 62)#define PIC_CTRL_RELAX_ORDER		(0x1ull << 61)#define PIC_CTRL_BUS_NUM(x)		((unsigned long long)(x) << 48)#define PIC_CTRL_BUS_NUM_MASK		(PIC_CTRL_BUS_NUM(0xff))#define PIC_CTRL_DEV_NUM(x)		((unsigned long long)(x) << 43)#define PIC_CTRL_DEV_NUM_MASK		(PIC_CTRL_DEV_NUM(0x1f))#define PIC_CTRL_FUN_NUM(x)		((unsigned long long)(x) << 40)#define PIC_CTRL_FUN_NUM_MASK		(PIC_CTRL_FUN_NUM(0x7))#define PIC_CTRL_PAR_EN_REQ		(0x1ull << 29)#define PIC_CTRL_PAR_EN_RESP		(0x1ull << 30)#define PIC_CTRL_PAR_EN_ATE		(0x1ull << 31)#define BRIDGE_CTRL_FLASH_WR_EN		(0x1ul << 31)   /* bridge only */#define BRIDGE_CTRL_EN_CLK50		(0x1 << 30)#define BRIDGE_CTRL_EN_CLK40		(0x1 << 29)#define BRIDGE_CTRL_EN_CLK33		(0x1 << 28)#define BRIDGE_CTRL_RST(n)		((n) << 24)#define BRIDGE_CTRL_RST_MASK		(BRIDGE_CTRL_RST(0xF))#define BRIDGE_CTRL_RST_PIN(x)		(BRIDGE_CTRL_RST(0x1 << (x)))#define BRIDGE_CTRL_IO_SWAP		(0x1 << 23)#define BRIDGE_CTRL_MEM_SWAP		(0x1 << 22)#define BRIDGE_CTRL_PAGE_SIZE		(0x1 << 21)#define BRIDGE_CTRL_SS_PAR_BAD		(0x1 << 20)#define BRIDGE_CTRL_SS_PAR_EN		(0x1 << 19)#define BRIDGE_CTRL_SSRAM_SIZE(n)	((n) << 17)#define BRIDGE_CTRL_SSRAM_SIZE_MASK	(BRIDGE_CTRL_SSRAM_SIZE(0x3))#define BRIDGE_CTRL_SSRAM_512K		(BRIDGE_CTRL_SSRAM_SIZE(0x3))#define BRIDGE_CTRL_SSRAM_128K		(BRIDGE_CTRL_SSRAM_SIZE(0x2))#define BRIDGE_CTRL_SSRAM_64K		(BRIDGE_CTRL_SSRAM_SIZE(0x1))#define BRIDGE_CTRL_SSRAM_1K		(BRIDGE_CTRL_SSRAM_SIZE(0x0))#define BRIDGE_CTRL_F_BAD_PKT		(0x1 << 16)#define BRIDGE_CTRL_LLP_XBAR_CRD(n)	((n) << 12)#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK	(BRIDGE_CTRL_LLP_XBAR_CRD(0xf))#define BRIDGE_CTRL_CLR_RLLP_CNT	(0x1 << 11)#define BRIDGE_CTRL_CLR_TLLP_CNT	(0x1 << 10)#define BRIDGE_CTRL_SYS_END		(0x1 << 9)#define BRIDGE_CTRL_PCI_SPEED		(0x3 << 4)#define BRIDGE_CTRL_BUS_SPEED(n)        ((n) << 4)#define BRIDGE_CTRL_BUS_SPEED_MASK      (BRIDGE_CTRL_BUS_SPEED(0x3))#define BRIDGE_CTRL_BUS_SPEED_33        0x00#define BRIDGE_CTRL_BUS_SPEED_66        0x10#define BRIDGE_CTRL_MAX_TRANS(n)	((n) << 4)#define BRIDGE_CTRL_MAX_TRANS_MASK	(BRIDGE_CTRL_MAX_TRANS(0x1f))#define BRIDGE_CTRL_WIDGET_ID(n)	((n) << 0)#define BRIDGE_CTRL_WIDGET_ID_MASK	(BRIDGE_CTRL_WIDGET_ID(0xf))/* Bridge Response buffer Error Upper Register bit fields definition */#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)#define BRIDGE_RESP_ERRRUPPR_BUFMASK	(0xFFFF)#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)	\			(((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \				BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)#define BRIDGE_RESP_ERRUPPR_DEVICE(x)	\			(((x) &	 BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \				 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)/* Bridge direct mapping register bits definition */#define BRIDGE_DIRMAP_W_ID_SHFT		20#define BRIDGE_DIRMAP_W_ID		(0xf << BRIDGE_DIRMAP_W_ID_SHFT)#define BRIDGE_DIRMAP_RMF_64		(0x1 << 18)#define BRIDGE_DIRMAP_ADD512		(0x1 << 17)#define BRIDGE_DIRMAP_OFF		(0x1ffff << 0)#define BRIDGE_DIRMAP_OFF_ADDRSHFT	(31)	/* lsbit of DIRMAP_OFF is xtalk address bit 31 *//* Bridge Arbitration register bits definition */#define BRIDGE_ARB_REQ_WAIT_TICK(x)	((x) << 16)#define BRIDGE_ARB_REQ_WAIT_TICK_MASK	BRIDGE_ARB_REQ_WAIT_TICK(0x3)#define BRIDGE_ARB_REQ_WAIT_EN(x)	((x) << 8)#define BRIDGE_ARB_REQ_WAIT_EN_MASK	BRIDGE_ARB_REQ_WAIT_EN(0xff)#define BRIDGE_ARB_FREEZE_GNT		(1 << 6)#define BRIDGE_ARB_HPRI_RING_B2		(1 << 5)#define BRIDGE_ARB_HPRI_RING_B1		(1 << 4)#define BRIDGE_ARB_HPRI_RING_B0		(1 << 3)#define BRIDGE_ARB_LPRI_RING_B2		(1 << 2)#define BRIDGE_ARB_LPRI_RING_B1		(1 << 1)
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