bridge.h

一个2.4.21版本的嵌入式linux内核

    bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
    bridgereg_t             _pad_0000C0;
#define b_pci_bus_timeout b_bus_timeout

    bridgereg_t             b_pci_cfg;              /* 0x0000CC */
    bridgereg_t             _pad_0000C8;

    bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
    bridgereg_t             _pad_0000D0;

    bridgereg_t             b_pci_err_lower;        /* 0x0000DC */
    bridgereg_t             _pad_0000D8;
    bridgereg_t		    _pad_0000E0[8];
#define b_gio_err_lower b_pci_err_lower
#define b_gio_err_upper b_pci_err_upper

    /* Interrupt				       0x000100-0x0001FF */
    bridgereg_t             b_int_status;           /* 0x000104 */
    bridgereg_t             _pad_000100;

    bridgereg_t             b_int_enable;           /* 0x00010C */
    bridgereg_t             _pad_000108;

    bridgereg_t             b_int_rst_stat;         /* 0x000114 */
    bridgereg_t             _pad_000110;

    bridgereg_t             b_int_mode;             /* 0x00011C */
    bridgereg_t             _pad_000118;

    bridgereg_t             b_int_device;           /* 0x000124 */
    bridgereg_t             _pad_000120;

    bridgereg_t             b_int_host_err;         /* 0x00012C */
    bridgereg_t             _pad_000128;

    struct {
        bridgereg_t             addr;               /* 0x0001{34,,,6C} */
        bridgereg_t             __pad;              /* 0x0001{30,,,68} */
    } b_int_addr[8];				    /* 0x000130 */

    bridgereg_t             b_err_int_view;         /* 0x000174 */
    bridgereg_t             _pad_000170;

    bridgereg_t             b_mult_int;             /* 0x00017c */
    bridgereg_t             _pad_000178;

    struct {
        bridgereg_t             intr;               /* 0x0001{84,,,BC} */
        bridgereg_t             __pad;              /* 0x0001{80,,,B8} */
    } b_force_always[8];			    /* 0x000180 */

    struct {
        bridgereg_t             intr;               /* 0x0001{C4,,,FC} */
        bridgereg_t             __pad;              /* 0x0001{C0,,,F8} */
    } b_force_pin[8];			    	    /* 0x0001C0 */

    /* Device					       0x000200-0x0003FF */
    struct {
        bridgereg_t             reg;                /* 0x0002{04,,,3C} */
        bridgereg_t             __pad;              /* 0x0002{00,,,38} */
    } b_device[8];				    /* 0x000200 */

    struct {
        bridgereg_t             reg;                /* 0x0002{44,,,7C} */
        bridgereg_t             __pad;              /* 0x0002{40,,,78} */
    } b_wr_req_buf[8];				    /* 0x000240 */

    struct {
        bridgereg_t             reg;                /* 0x0002{84,,,8C} */
        bridgereg_t             __pad;              /* 0x0002{80,,,88} */
    } b_rrb_map[2];				    /* 0x000280 */
#define	b_even_resp	b_rrb_map[0].reg	    /* 0x000284 */
#define	b_odd_resp	b_rrb_map[1].reg	    /* 0x00028C */

    bridgereg_t             b_resp_status;          /* 0x000294 */
    bridgereg_t             _pad_000290;

    bridgereg_t             b_resp_clear;           /* 0x00029C */
    bridgereg_t             _pad_000298;

    bridgereg_t		    _pad_0002A0[24];

    /* Xbridge only */
    struct {
	bridgereg_t	        upper;              /* 0x0003{04,,,F4} */
	bridgereg_t             __pad1;		    /* 0x0003{00,,,F0} */
	bridgereg_t             lower;              /* 0x0003{0C,,,FC} */
	bridgereg_t             __pad2;             /* 0x0003{08,,,F8} */
    } b_buf_addr_match[16];

    /* Performance Monitor Registers (even only) */
    struct {
        bridgereg_t             flush_w_touch;      /* 0x000404,,,5C4 */
        bridgereg_t             __pad1;             /* 0x000400,,,5C0 */

        bridgereg_t             flush_wo_touch;     /* 0x00040C,,,5CC */
        bridgereg_t             __pad2;             /* 0x000408,,,5C8 */

        bridgereg_t             inflight;           /* 0x000414,,,5D4 */
        bridgereg_t             __pad3;             /* 0x000410,,,5D0 */

        bridgereg_t             prefetch;           /* 0x00041C,,,5DC */
        bridgereg_t             __pad4;             /* 0x000418,,,5D8 */

        bridgereg_t             total_pci_retry;    /* 0x000424,,,5E4 */
        bridgereg_t             __pad5;             /* 0x000420,,,5E0 */

        bridgereg_t             max_pci_retry;      /* 0x00042C,,,5EC */
        bridgereg_t             __pad6;             /* 0x000428,,,5E8 */

        bridgereg_t             max_latency;        /* 0x000434,,,5F4 */
        bridgereg_t             __pad7;             /* 0x000430,,,5F0 */

        bridgereg_t             clear_all;          /* 0x00043C,,,5FC */
        bridgereg_t             __pad8;             /* 0x000438,,,5F8 */
    } b_buf_count[8];

    char                    _pad_000600[0x010000 - 0x000600];

    /*
     * The Xbridge has 1024 internal ATE's and the Bridge has 128.
     * Make enough room for the Xbridge ATE's and depend on runtime
     * checks to limit access to bridge ATE's.
     */

    /* Internal Address Translation Entry RAM	       0x010000-0x011fff */
    union {
	bridge_ate_t		wr;		/* write-only */
	struct {
	    bridgereg_t             rd;         /* read-only */
            bridgereg_t             _p_pad;
	}			hi;
    }			    b_int_ate_ram[XBRIDGE_INTERNAL_ATES];

#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd

    /* the xbridge read path for internal ates starts at 0x12000.
     * I don't believe we ever try to read the ates.
     */
    /* Internal Address Translation Entry RAM LOW       0x012000-0x013fff */
    struct {
	bridgereg_t             rd; 
        bridgereg_t             _p_pad;
    }			    xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];

    char		    _pad_014000[0x20000 - 0x014000];

    /* PCI Device Configuration Spaces		       0x020000-0x027FFF */
    union {				/* make all access sizes available. */
	uchar_t			c[0x1000 / 1];
	uint16_t		s[0x1000 / 2];
	uint32_t		l[0x1000 / 4];
	uint64_t		d[0x1000 / 8];
	union {
	    uchar_t		c[0x100 / 1];
	    uint16_t		s[0x100 / 2];
	    uint32_t		l[0x100 / 4];
	    uint64_t		d[0x100 / 8];
	}			f[8];
    } b_type0_cfg_dev[8];			    /* 0x020000 */

    /* PCI Type 1 Configuration Space		       0x028000-0x028FFF */
    union {				/* make all access sizes available. */
	uchar_t			c[0x1000 / 1];
	uint16_t		s[0x1000 / 2];
	uint32_t		l[0x1000 / 4];
	uint64_t		d[0x1000 / 8];
        union {
            uchar_t         c[0x100 / 1];
            uint16_t        s[0x100 / 2];
            uint32_t        l[0x100 / 4];
            uint64_t        d[0x100 / 8];
	} f[8];
    } b_type1_cfg;				    /* 0x028000-0x029000 */

    char		    _pad_029000[0x007000];  /* 0x029000-0x030000 */

    /* PCI Interrupt Acknowledge Cycle		       0x030000 */
    union {
	uchar_t			c[8 / 1];
	uint16_t		s[8 / 2];
	uint32_t		l[8 / 4];
	uint64_t		d[8 / 8];
    } b_pci_iack;				    /* 0x030000 */

    uchar_t		    _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */

    /* External Address Translation Entry RAM	       0x080000-0x0FFFFF */
    bridge_ate_t	    b_ext_ate_ram[0x10000];

    /* Reserved					       0x100000-0x1FFFFF */
    char		    _pad_100000[0x200000-0x100000];

    /* PCI/GIO Device Spaces			       0x200000-0xBFFFFF */
    union {				/* make all access sizes available. */
	uchar_t			c[0x100000 / 1];
	uint16_t		s[0x100000 / 2];
	uint32_t		l[0x100000 / 4];
	uint64_t		d[0x100000 / 8];
    } b_devio_raw[10];			/* 0x200000 */

    /* b_devio macro is a bit strange; it reflects the
     * fact that the Bridge ASIC provides 2M for the
     * first two DevIO windows and 1M for the other six.
     */
#define b_devio(n)	b_devio_raw[((n)<2)?(n*2):(n+2)]

    /* External Flash Proms 1,0			       0xC00000-0xFFFFFF */
    union {				/* make all access sizes available. */
	uchar_t			c[0x400000 / 1];	/* read-only */
	uint16_t		s[0x400000 / 2];	/* read-write */
	uint32_t		l[0x400000 / 4];	/* read-only */
	uint64_t		d[0x400000 / 8];	/* read-only */
    } b_external_flash;			/* 0xC00000 */
} bridge_t;

#endif	/* CONFIG_IA64_SGI_SN1 */


#define berr_field	berr_un.berr_st
#endif				/* __ASSEMBLY__ */

/*
 * The values of these macros can and should be crosschecked
 * regularly against the offsets of the like-named fields
 * within the "bridge_t" structure above.
 */

/* Byte offset macros for Bridge internal registers */

#define BRIDGE_WID_ID		WIDGET_ID
#define BRIDGE_WID_STAT		WIDGET_STATUS
#define BRIDGE_WID_ERR_UPPER	WIDGET_ERR_UPPER_ADDR
#define BRIDGE_WID_ERR_LOWER	WIDGET_ERR_LOWER_ADDR
#define BRIDGE_WID_CONTROL	WIDGET_CONTROL
#define BRIDGE_WID_REQ_TIMEOUT	WIDGET_REQ_TIMEOUT
#define BRIDGE_WID_INT_UPPER	WIDGET_INTDEST_UPPER_ADDR
#define BRIDGE_WID_INT_LOWER	WIDGET_INTDEST_LOWER_ADDR
#define BRIDGE_WID_ERR_CMDWORD	WIDGET_ERR_CMD_WORD
#define BRIDGE_WID_LLP		WIDGET_LLP_CFG
#define BRIDGE_WID_TFLUSH	WIDGET_TFLUSH

#define BRIDGE_WID_AUX_ERR	0x00005C	/* Aux Error Command Word */
#define BRIDGE_WID_RESP_UPPER	0x000064	/* Response Buf Upper Addr */
#define BRIDGE_WID_RESP_LOWER	0x00006C	/* Response Buf Lower Addr */
#define BRIDGE_WID_TST_PIN_CTRL 0x000074	/* Test pin control */

#define BRIDGE_DIR_MAP		0x000084	/* Direct Map reg */

/* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */
#define BRIDGE_RAM_PERR 	0x000094	/* SSRAM Parity Error */
#define BRIDGE_MAP_FAULT	0x000094	/* Map Fault */

#define BRIDGE_ARB		0x0000A4	/* Arbitration Priority reg */

#define BRIDGE_NIC		0x0000B4	/* Number In A Can */

#define BRIDGE_BUS_TIMEOUT	0x0000C4	/* Bus Timeout Register */
#define BRIDGE_PCI_BUS_TIMEOUT	BRIDGE_BUS_TIMEOUT
#define BRIDGE_PCI_CFG		0x0000CC	/* PCI Type 1 Config reg */
#define BRIDGE_PCI_ERR_UPPER	0x0000D4	/* PCI error Upper Addr */
#define BRIDGE_PCI_ERR_LOWER	0x0000DC	/* PCI error Lower Addr */

#define BRIDGE_INT_STATUS	0x000104	/* Interrupt Status */
#define BRIDGE_INT_ENABLE	0x00010C	/* Interrupt Enables */
#define BRIDGE_INT_RST_STAT	0x000114	/* Reset Intr Status */
#define BRIDGE_INT_MODE		0x00011C	/* Interrupt Mode */
#define BRIDGE_INT_DEVICE	0x000124	/* Interrupt Device */
#define BRIDGE_INT_HOST_ERR	0x00012C	/* Host Error Field */

#define BRIDGE_INT_ADDR0	0x000134	/* Host Address Reg */
#define BRIDGE_INT_ADDR_OFF	0x000008	/* Host Addr offset (1..7) */
#define BRIDGE_INT_ADDR(x)	(BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)

#define BRIDGE_INT_VIEW		0x000174	/* Interrupt view */
#define BRIDGE_MULTIPLE_INT	0x00017c	/* Multiple interrupt occurred */

#define BRIDGE_FORCE_ALWAYS0	0x000184	/* Force an interrupt (always)*/
#define BRIDGE_FORCE_ALWAYS_OFF 0x000008	/* Force Always offset */
#define BRIDGE_FORCE_ALWAYS(x)  (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF)

#define BRIDGE_FORCE_PIN0	0x0001c4	/* Force an interrupt */
#define BRIDGE_FORCE_PIN_OFF 	0x000008	/* Force Pin offset */
#define BRIDGE_FORCE_PIN(x)  (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF)

#define BRIDGE_DEVICE0		0x000204	/* Device 0 */
#define BRIDGE_DEVICE_OFF	0x000008	/* Device offset (1..7) */
#define BRIDGE_DEVICE(x)	(BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)

#define BRIDGE_WR_REQ_BUF0	0x000244	/* Write Request Buffer 0 */
#define BRIDGE_WR_REQ_BUF_OFF	0x000008	/* Buffer Offset (1..7) */
#define BRIDGE_WR_REQ_BUF(x)	(BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)

#define BRIDGE_EVEN_RESP	0x000284	/* Even Device Response Buf */
#define BRIDGE_ODD_RESP		0x00028C	/* Odd Device Response Buf */

#define BRIDGE_RESP_STATUS	0x000294	/* Read Response Status reg */
#define BRIDGE_RESP_CLEAR	0x00029C	/* Read Response Clear reg */

#define BRIDGE_BUF_ADDR_UPPER0	0x000304
#define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010	/* PCI Buffer Upper Offset */
#define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF)

#define BRIDGE_BUF_ADDR_LOWER0	0x00030c
#define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010	/* PCI Buffer Upper Offset */
#define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF)

/* 
 * Performance Monitor Registers.
 *
 * The Performance registers are those registers which are associated with
 * monitoring the performance of PCI generated reads to the host environ
 * ment. Because of the size of the register file only the even registers
 * were instrumented.
 */

#define BRIDGE_BUF_OFF 0x40
#define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF))

/*
 * Buffer (x) Flush Count with Data Touch Register.
 *
 * This counter is incremented each time the corresponding response buffer
 * is flushed after at least a single data element in the buffer is used.
 * A word write to this address clears the count.
 */

#define BRIDGE_BUF_0_FLUSH_TOUCH  0x000404
#define BRIDGE_BUF_2_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1)
#define BRIDGE_BUF_4_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2)
#define BRIDGE_BUF_6_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3)
#define BRIDGE_BUF_8_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4)
#define BRIDGE_BUF_10_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5)
#define BRIDGE_BUF_12_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6)
#define BRIDGE_BUF_14_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7)

/*