pci_defs.h

一个2.4.21版本的嵌入式linux内核

 * determine the offset.  Each capability block contains a capability ID, a
 * ``pointer'' to the next capability (another offset where a zero terminates
 * the list) and capability-specific data.  Each capability block starts with
 * the capability ID and the ``next capability pointer.''  All data following
 * this are capability-dependent.
 */
#define PCI_CAP_ID		0x00		/* Capability ID (1B) */
#define PCI_CAP_PTR		0x01		/* Capability ``pointer'' (1B) */

/* PCI Capability IDs */
#define	PCI_CAP_PM		0x01		/* PCI Power Management */
#define	PCI_CAP_AGP		0x02		/* Accelerated Graphics Port */
#define	PCI_CAP_VPD		0x03		/* Vital Product Data (VPD) */
#define	PCI_CAP_SID		0x04		/* Slot Identification */
#define PCI_CAP_MSI		0x05		/* Message Signaled Intr */
#define	PCI_CAP_HS		0x06		/* CompactPCI Hot Swap */
#define	PCI_CAP_PCIX		0x07		/* PCI-X */
#define PCI_CAP_ID_HT		0x08		/* HyperTransport */


/* PIO interface macros */

#ifndef IOC3_EMULATION

#define PCI_INB(x)          (*((volatile char*)x))
#define PCI_INH(x)          (*((volatile short*)x))
#define PCI_INW(x)          (*((volatile int*)x))
#define PCI_OUTB(x,y)       (*((volatile char*)x) = y)
#define PCI_OUTH(x,y)       (*((volatile short*)x) = y)
#define PCI_OUTW(x,y)       (*((volatile int*)x) = y)

#else

extern uint pci_read(void * address, int type);
extern void pci_write(void * address, int data, int type);

#define BYTE   1
#define HALF   2
#define WORD   4

#define PCI_INB(x)          pci_read((void *)(x),BYTE)
#define PCI_INH(x)          pci_read((void *)(x),HALF)
#define PCI_INW(x)          pci_read((void *)(x),WORD)
#define PCI_OUTB(x,y)       pci_write((void *)(x),(y),BYTE)
#define PCI_OUTH(x,y)       pci_write((void *)(x),(y),HALF)
#define PCI_OUTW(x,y)       pci_write((void *)(x),(y),WORD)

#endif /* !IOC3_EMULATION */
						/* effects on reads, merges */

/*
 * Definition of address layouts for PCI Config mechanism #1
 * XXX- These largely duplicate PCI_TYPE1 constants at the top
 * of the file; the two groups should probably be combined.
 */

#define CFG1_ADDR_REGISTER_MASK		0x000000fc
#define CFG1_ADDR_FUNCTION_MASK		0x00000700
#define CFG1_ADDR_DEVICE_MASK		0x0000f800
#define CFG1_ADDR_BUS_MASK		0x00ff0000

#define CFG1_REGISTER_SHIFT		2
#define CFG1_FUNCTION_SHIFT		8
#define CFG1_DEVICE_SHIFT		11
#define CFG1_BUS_SHIFT			16

#ifdef CONFIG_SGI_IP32
 /* Definitions related to IP32 PCI Bridge policy
  * XXX- should probaly be moved to a mace-specific header
  */
#define PCI_CONFIG_BITS			0xfe0085ff
#define	PCI_CONTROL_MRMRA_ENABLE	0x00000800
#define PCI_FIRST_IO_ADDR		0x1000
#define PCI_IO_MAP_INCR			0x1000
#endif /* CONFIG_SGI_IP32 */

/*
 * Class codes
 */
#define PCI_CFG_CLASS_PRE20	0x00
#define PCI_CFG_CLASS_STORAGE	0x01
#define PCI_CFG_CLASS_NETWORK	0x02
#define PCI_CFG_CLASS_DISPLAY	0x03
#define PCI_CFG_CLASS_MMEDIA	0x04
#define PCI_CFG_CLASS_MEMORY	0x05
#define PCI_CFG_CLASS_BRIDGE	0x06
#define PCI_CFG_CLASS_COMM	0x07
#define PCI_CFG_CLASS_BASE	0x08
#define PCI_CFG_CLASS_INPUT	0x09
#define PCI_CFG_CLASS_DOCK	0x0A
#define PCI_CFG_CLASS_PROC	0x0B
#define PCI_CFG_CLASS_SERIALBUS	0x0C
#define PCI_CFG_CLASS_OTHER	0xFF

/*
 * Important Subclasses
 */
#define PCI_CFG_SUBCLASS_BRIDGE_HOST	0x00
#define PCI_CFG_SUBCLASS_BRIDGE_ISA	0x01
#define PCI_CFG_SUBCLASS_BRIDGE_EISA	0x02
#define PCI_CFG_SUBCLASS_BRIDGE_MC	0x03
#define PCI_CFG_SUBCLASS_BRIDGE_PCI	0x04
#define PCI_CFG_SUBCLASS_BRIDGE_PCMCIA	0x05
#define PCI_CFG_SUBCLASS_BRIDGE_NUBUS	0x06
#define PCI_CFG_SUBCLASS_BRIDGE_CARDBUS	0x07
#define PCI_CFG_SUBCLASS_BRIDGE_OTHER	0x80

#ifndef __ASSEMBLY__

/*
 * PCI config space definition
 */
typedef volatile struct pci_cfg_s {
	uint16_t	dev_id;
	uint16_t	vendor_id;
	uint16_t	status;
	uint16_t	cmd;
	uchar_t		class;
	uchar_t		sub_class;
	uchar_t		prog_if;
	uchar_t		rev;
	uchar_t		bist;
	uchar_t		hdr_type;
	uchar_t		lt;
	uchar_t		line_size;
	uint32_t	bar[6];
	uint32_t	cardbus;
	uint16_t	subsys_dev_id;
	uint16_t	subsys_vendor_id;
	uint32_t	exp_rom;
	uint32_t	res[2];
	uchar_t		max_lat;
	uchar_t		min_gnt;
	uchar_t		int_pin;
	uchar_t		int_line;
} pci_cfg_t;

/*
 * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs)
 */
typedef volatile struct pci_cfg1_s {
	uint16_t	dev_id;
	uint16_t	vendor_id;
	uint16_t	status;
	uint16_t	cmd;
	uchar_t		class;
	uchar_t		sub_class;
	uchar_t		prog_if;
	uchar_t		rev;
	uchar_t		bist;
	uchar_t		hdr_type;
	uchar_t		lt;
	uchar_t		line_size;
	uint32_t	bar[2];
	uchar_t		slt;
	uchar_t		sub_bus_num;
	uchar_t		snd_bus_num;
	uchar_t		pri_bus_num;
	uint16_t	snd_status;
	uchar_t		io_limit;
	uchar_t		io_base;
	uint16_t	mem_limit;
	uint16_t	mem_base;
	uint16_t	pmem_limit;
	uint16_t	pmem_base;
	uint32_t	pmem_limit_upper;
	uint32_t	pmem_base_upper;
	uint16_t	io_limit_upper;
	uint16_t	io_base_upper;
	uint32_t	res;
	uint32_t	exp_rom;
	uint16_t	ppb_control;
	uchar_t		int_pin;
	uchar_t		int_line;
} pci_cfg1_t;

/*
 * PCI-X Capability
 */
typedef volatile struct cap_pcix_cmd_reg_s {
	uint16_t	reserved1:              9,
			max_split:		3,
			max_mem_read_cnt:	2,
			enable_relaxed_order:	1,
			data_parity_enable:	1;
} cap_pcix_cmd_reg_t;

typedef volatile struct cap_pcix_stat_reg_s {
	uint32_t	reserved1:		2,
			split_complt_err:	1,
			max_cum_read:		3,
			max_out_split:		3,
			max_mem_read_cnt:	2,
			device_complex:		1,
			unexpect_split_complt:	1,
			split_complt_discard:	1,
			mhz133_capable:		1,
			bit64_device:		1,
			bus_num:		8,
			dev_num:		5,
			func_num:		3;
} cap_pcix_stat_reg_t;

typedef volatile struct cap_pcix_type0_s {
	cap_pcix_cmd_reg_t	pcix_type0_command;
	uchar_t			pcix_cap_nxt;
	uchar_t			pcix_cap_id;
	cap_pcix_stat_reg_t	pcix_type0_status;
} cap_pcix_type0_t;

#endif	/* __ASSEMBLY__ */
#endif /* _ASM_SN_PCI_PCI_DEFS_H */