init.c

一个2.4.21版本的嵌入式linux内核

   if(HwDeviceExtension->jChipType == SIS_550) {
       /* SetDRAMConfig begin */
/*     SiS_SetReg1(SiS_Pr->SiS_P3c4,0x12,SR12);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,SR13);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,SR14);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,SR16);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x17,SR17);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x18,SR18);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x19,SR19);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x1A,SR1A);   */
       /* SetDRAMConfig end */
   }
#endif

#ifdef SIS300
   if(HwDeviceExtension->jChipType == SIS_300) {
       	if (HwDeviceExtension->bSkipDramSizing == TRUE) {
/*       	SiS_SetDRAMModeRegister(ROMAddr,HwDeviceExtension);
         	temp = (HwDeviceExtension->pSR)->jVal;
         	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,temp);
         	temp = (HwDeviceExtension->pSR)->jVal;
         	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,temp);   */
       } else {
#ifdef TC
         	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,SR13);
         	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,SR14);
         	SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x15,0xFF,0x04);
#else
         	SiS_SetDRAMSize_300(SiS_Pr, HwDeviceExtension);
         	SiS_SetDRAMSize_300(SiS_Pr, HwDeviceExtension);
#endif
       }
   }
   if((HwDeviceExtension->jChipType==SIS_540)||
      (HwDeviceExtension->jChipType==SIS_630)||
      (HwDeviceExtension->jChipType==SIS_730)) {
#if 0
     	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x12,SR12);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,SR13);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,SR14);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,SR16);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x17,SR17);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x18,SR18);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x19,SR19);
       	SiS_SetReg1(SiS_Pr->SiS_P3c4,0x1A,SR1A);
#endif
   }
/* SetDRAMSize end */
#endif /* SIS300 */

   /* Set default Ext2Regs */
#if 0
   AGP=1;
   temp=(UCHAR)SiS_GetReg1(SiS_Pr->SiS_P3c4,0x3A);
   temp &= 0x30;
   if(temp == 0x30) AGP=0;
   if(AGP == 0) *SiS_Pr->pSiS_SR21 &= 0xEF;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x21,*SiS_Pr->pSiS_SR21);
   if(AGP == 1) *SiS_Pr->pSiS_SR22 &= 0x20;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x22,*SiS_Pr->pSiS_SR22);
#endif
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x21,*SiS_Pr->pSiS_SR21);
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x22,*SiS_Pr->pSiS_SR22);

#if 0
   SiS_SetReg3(SiS_Pr->SiS_P3c6,0xff);
   SiS_ClearDAC(SiS_Pr, SiS_Pr->SiS_P3c8);
#endif

#ifdef LINUXBIOS   /* TW: This is not needed for our purposes */
   SiS_DetectMonitor(SiS_Pr, HwDeviceExtension,BaseAddr);    /* Sense CRT1 */
   SiS_GetSenseStatus(SiS_Pr, HwDeviceExtension,ROMAddr);    /* Sense CRT2 */
#endif

   return(TRUE);
}

void
SiS_Set_LVDS_TRUMPION(SiS_Private *SiS_Pr, PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
  USHORT temp = 0;

#ifdef SiS300
  if((HwDeviceExtension->jChipType == SIS_540) ||
     (HwDeviceExtension->jChipType == SIS_630) ||
     (HwDeviceExtension->jChipType == SIS_730)) {
        /* TW: Read POWER_ON_TRAP and copy to CR37 */
    	temp = (UCHAR)SiS_GetReg1(SiS_Pr->SiS_P3c4,0x1A);
    	temp = (temp & 0xE0) >> 4;
   	SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x37,0xF1,temp);
  }
#endif
#ifdef SIS315H
  if((HwDeviceExtension->jChipType == SIS_650) ||
     (HwDeviceExtension->jChipType == SIS_740) ||
     (HwDeviceExtension->jChipType == SIS_330)) {
#if 0 /* TW: This is not required */
        /* TW: Read POWER_ON_TRAP and copy to CR37 */
    	temp = (UCHAR)SiS_GetReg1(SiS_Pr->SiS_P3c4,0x1A);
    	temp = (temp & 0xE0) >> 4;
   	SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x37,0xF1,temp);
#endif
  }
#endif

   SiSSetLVDSetc(SiS_Pr, HwDeviceExtension, 0);
}

/* ===============  SiS 300 dram sizing begin  =============== */
#ifdef SIS300
void
SiS_SetDRAMSize_300(SiS_Private *SiS_Pr, PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
   ULONG   FBAddr = (ULONG)HwDeviceExtension->pjVideoMemoryAddress;
   USHORT  SR13, SR14=0, buswidth, Done;
   SHORT   i, j, k;
   USHORT  data, TotalCapacity, PhysicalAdrOtherPage=0;
   ULONG   Addr;
   UCHAR   temp;
   int     PseudoRankCapacity, PseudoTotalCapacity, PseudoAdrPinCount;
   int     RankCapacity, AdrPinCount, BankNumHigh, BankNumMid, MB2Bank;
   int     PageCapacity, PhysicalAdrHigh, PhysicalAdrHalfPage;

   SiSSetMode(SiS_Pr, HwDeviceExtension, 0x2e);

   SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x20);        /* Turn OFF Display  */

   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,0x00);
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,0xBF);

   buswidth = SiS_ChkBUSWidth_300(SiS_Pr, FBAddr);

   MB2Bank = 16;
   Done = 0;
   for(i=6; i>=0; i--) {
      if(Done == 1) break;
      PseudoRankCapacity = 1 << i;
      for(j=4; j>=1; j--) {
         if(Done == 1) break;
         PseudoTotalCapacity = PseudoRankCapacity * j;
         PseudoAdrPinCount = 15 - j;
         if(PseudoTotalCapacity <= 64) {
            for(k=0; k<=16; k++) {
               if(Done == 1) break;
               RankCapacity = buswidth * SiS_DRAMType[k][3];
               AdrPinCount = SiS_DRAMType[k][2] + SiS_DRAMType[k][0];
               if(RankCapacity == PseudoRankCapacity)
                 if(AdrPinCount <= PseudoAdrPinCount) {
                    if(j == 3) {             /* Rank No */
                       BankNumHigh = RankCapacity * MB2Bank * 3 - 1;
                       BankNumMid = RankCapacity * MB2Bank * 1 - 1;
                    } else {
                       BankNumHigh = RankCapacity * MB2Bank * j - 1;
                       BankNumMid = RankCapacity * MB2Bank * j / 2 - 1;
                    }
                    PageCapacity = (1 << SiS_DRAMType[k][1]) * buswidth * 4;
                    PhysicalAdrHigh = BankNumHigh;
                    PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity;
                    PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh;
                    /* Write data */
                    /*Test*/
                    SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x15,0xFB);
                    SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x15,0x04);
                    /*/Test*/
                    TotalCapacity = SiS_DRAMType[k][3] * buswidth;
                    SR13 = SiS_DRAMType[k][4];
                    if(buswidth == 4) SR14 = (TotalCapacity - 1) | 0x80;
                    if(buswidth == 2) SR14 = (TotalCapacity - 1) | 0x40;
                    if(buswidth == 1) SR14 = (TotalCapacity - 1) | 0x00;
                    SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,SR13);
                    SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,SR14);

                    Addr = FBAddr + (BankNumHigh) * 64 * 1024 + PhysicalAdrHigh;
                    *((USHORT *)(Addr)) = (USHORT)PhysicalAdrHigh;
                    Addr = FBAddr + (BankNumMid) * 64 * 1024 + PhysicalAdrHigh;
                    *((USHORT *)(Addr)) = (USHORT)BankNumMid;
                    Addr = FBAddr + (BankNumHigh) * 64 * 1024 + PhysicalAdrHalfPage;
                    *((USHORT *)(Addr)) = (USHORT)PhysicalAdrHalfPage;
                    Addr = FBAddr + (BankNumHigh) * 64 * 1024 + PhysicalAdrOtherPage;
                    *((USHORT *)(Addr)) = PhysicalAdrOtherPage;

                    /* Read data */
                    Addr = FBAddr + (BankNumHigh) * 64 * 1024 + PhysicalAdrHigh;
                    data = *((USHORT *)(Addr));
                    if(data == PhysicalAdrHigh) Done = 1;
                 }  /* if struct */
            }  /* for loop (k) */
         }  /* if struct */
      }  /* for loop (j) */
   }  /* for loop (i) */
}

USHORT
SiS_ChkBUSWidth_300(SiS_Private *SiS_Pr, ULONG FBAddress)
{
   PULONG  pVideoMemory;

   pVideoMemory = (PULONG)FBAddress;

   pVideoMemory[0] = 0x01234567L;
   pVideoMemory[1] = 0x456789ABL;
   pVideoMemory[2] = 0x89ABCDEFL;
   pVideoMemory[3] = 0xCDEF0123L;
   if (pVideoMemory[3]==0xCDEF0123L) {  /* Channel A 128bit */
     return(4);
   }
   if (pVideoMemory[1]==0x456789ABL) {  /* Channel B 64bit */
     return(2);
   }
   return(1);
}
#endif
/* ===============  SiS 300 dram sizing end    =============== */

/* ============  SiS 310/325 dram sizing begin  ============== */
#ifdef SIS315H

/* TW: Moved Get310DRAMType further down */

void
SiS_Delay15us(SiS_Private *SiS_Pr, ULONG ulMicrsoSec)
{
}

void
SiS_SDR_MRS(SiS_Private *SiS_Pr, )
{
   USHORT  data;

   data = SiS_GetReg1(SiS_Pr->SiS_P3c4,0x16);
   data &= 0x3F;          		        /* SR16 D7=0, D6=0 */
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);   	/* enable mode register set(MRS) low */
   SiS_Delay15us(SiS_Pr, 0x100);
   data |= 0x80;          		        /* SR16 D7=1, D6=0 */
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);   	/* enable mode register set(MRS) high */
   SiS_Delay15us(SiS_Pr, 0x100);
}

void
SiS_DDR_MRS(SiS_Private *SiS_Pr)
{
   USHORT  data;

   /* SR16 <- 1F,DF,2F,AF */

   /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
   data=SiS_GetReg1(SiS_Pr->SiS_P3c4,0x16);
   data &= 0x0F;
   data |= 0x10;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);

   if (!(SiS_Pr->SiS_SR15[1][SiS_Pr->SiS_RAMType] & 0x10))
     data &= 0x0F;

   /* SR16 D7=1,D6=1 */
   data |= 0xC0;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);
   
   /* SR16 D7=1,D6=0,D5=1,D4=0 */
   data &= 0x0F;
   data |= 0x20;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);
   if (!(SiS_Pr->SiS_SR15[1][SiS_Pr->SiS_RAMType] & 0x10))
     data &= 0x0F;

   /* SR16 D7=1 */
   data |= 0x80;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);
}

void
SiS_SetDRAMModeRegister(SiS_Private *SiS_Pr, UCHAR *ROMAddr, PSIS_HW_DEVICE_INFO HwDeviceExtensi