8253xini.c

一个2.4.21版本的嵌入式linux内核

}

/* 8x20 type functions */

static void DisableESCC8Interrupts(SAB_CHIP *chipptr)
{
	unsigned int regbase;		/* a lot more to do for ESCC8 */
	
	regbase = (unsigned int) chipptr->c_regs;
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_A); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_B); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_C); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_D); /* All interrupts off */
}

static SAB_CHIP* CreateESCC8(SAB_BOARD *bptr, unsigned int offset)
{
	SAB_CHIP *cptr;
	unsigned int regbase;
	
	printk(KERN_ALERT 
	       "auraXX20n: creating ESCC8 structure on board %p at offset %x.\n",
	       bptr, offset);
	
	cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL);
	if(cptr == NULL)
	{
		printk(KERN_ALERT
		       "auraXX20n: Failed to create ESCC8 structure on board %p at offset %x.\n",
		       bptr, offset);
		return NULL;
	}
	memset(cptr, 0, sizeof(SAB_CHIP));
	cptr->chip_type = ESCC8;
	cptr->c_board = bptr;
	cptr->c_cim = NULL;
	cptr->c_chipno = (offset ? 1 : 0); /* no card actually has 2 ESCC8s on it */
	cptr->c_revision = 
		(readb(((char *)bptr->virtbaseaddress2) + offset + SAB85232_REG_VSTR) & 
		 SAB82532_VSTR_VN_MASK);
	cptr->c_nports = 8;
	cptr->c_portbase = NULL;	/* used for the list of ports associated
					   with this chip
					*/
	cptr->next = AuraChipRoot;
	AuraChipRoot = cptr;
	cptr->next_by_board = bptr->board_chipbase;
	bptr->board_chipbase = cptr;
	printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n",
	       cptr->c_chipno, bptr, cptr->c_revision);
	
	/* lets set up the generic parallel
	 * port register which is used to
	 * control signaling and other stuff*/
	
	/* SAB82538 4 8-bits parallel ports
	 * To summarize the use of the parallel port:
	 *                    RS-232
	 * Parallel port A -- TxClkdir control	(output) ports 0 - 7
	 * Parallel port B -- DTR		(output) ports 0 - 7
	 * Parallel port C -- DSR		(input)  ports 0 - 7
	 * Parallel port D -- driver power down 	(output) drivers 0 - 3
	 *
	 * Note port D is not used on recent boards
	 */
	
	regbase = (unsigned int)(((char *)bptr->virtbaseaddress2) + offset);
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port A (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_A, SAB82538_REG_PIM_A, SAB82538_REG_PVR_A));
	
	/* Configuring Parallel Port A  (Clkdir)*/
	writeb(0x0,((unsigned char *)regbase) + SAB82538_REG_PCR_A);  /* All output bits */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_A); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PVR_A);  /* All low */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port B (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_B,SAB82538_REG_PIM_B,SAB82538_REG_PVR_B));
	
	writeb(0x0,((unsigned char *)regbase) + SAB82538_REG_PCR_B);  /* All output bits */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_B); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PVR_B);  /* All low */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port C (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_C, SAB82538_REG_PIM_C, SAB82538_REG_PVR_C));
	
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PCR_C);  /* All intput bits */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_C); /* All interrupts off */
	/* don't set port value register on input register */
	
	/* Configuring Parallel Port D */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port D (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_D, SAB82538_REG_PIM_D, SAB82538_REG_PVR_D));
	writeb(0x0f,((unsigned char *)regbase) + SAB82538_REG_PCR_D);  /* 4 input  bits */
	writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_D); /* All interrupts off */
	/* don't set port value register on input register */
	
	/* The priority rotation thing */
	
	DEBUGPRINT((KERN_ALERT "Setting IVA (0x%x +  0x%x = 0x%x\n", regbase,
		    SAB82532_REG_IVA, regbase + SAB82532_REG_IVA));
	
	writeb(SAB82538_IVA_ROT, ((unsigned char *)regbase) + SAB82532_REG_IVA); 
	
	cptr->c_regs = (void*) regbase;
	cptr->int_disable = DisableESCC8Interrupts;
	return cptr;
}

static void DisableESCC8InterruptsFromCIM(SAB_CHIP *chipptr)
{
	unsigned int regbase;		/* a lot more to do for ESCC8 */
	
	regbase = (unsigned int) chipptr->c_regs;
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_A)); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_B)); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_C)); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_D)); /* All interrupts off */
}

static void CreateESCC8Port(SAB_CHIP *cptr, unsigned int portno, unsigned int function)
{
	SAB_BOARD *bptr;
	SAB_PORT  *pptr;
	extern void sab8253x_setup_ttyport(struct sab_port *p_port) ;
	
	++NumSab8253xPorts;
	bptr = cptr->c_board;
	pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL);
	if(pptr == NULL)
	{
		printk(KERN_ALERT
		       "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n",
		       cptr, bptr);
		return;
	}
	memset(pptr, 0, sizeof(SAB_PORT));
	DEBUGPRINT
		((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n", 
		  portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number));
	pptr->portno = portno;
	pptr->chip=cptr;
	pptr->board=bptr;
	pptr->open_type=OPEN_NOT;
	pptr->is_console=0;
	pptr->regs=
		(union sab82532_regs *)
		(((unsigned int)cptr->c_regs) +
		 (portno * SAB82538_REG_SIZE));
	pptr->type = cptr->c_revision;
	pptr->function = function;
	
	pptr->irq = bptr->b_irq;
	
	pptr->dsr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_C; 
	pptr->dsr.mask = 0x1 << portno;
	pptr->dsr.inverted = 1;
	pptr->dsr.irq=PIS_IDX;	/* need to check this constant */
	pptr->dsr.irqmask=0x1 << portno;
	pptr->dsr.cnst = 0;
	
	pptr->txclkdir.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_A;
	pptr->txclkdir.mask = 0x1 << portno;
	/* NOTE: Early 8 ports  boards had different tx clkdir sense */
	pptr->txclkdir.inverted = 1;
	
	pptr->dtr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_B;
	pptr->dtr.mask = 0x1 << portno;
	pptr->dtr.inverted = 1;
	pptr->dtr.cnst = 0;
	
	pptr ->dcd.reg = (unsigned char *)&(VSTR);
	
	DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr ->dcd.reg));
	
	pptr->dcd.mask = SAB82532_VSTR_CD;
	pptr->dcd.inverted = 1;
	pptr->dcd.irq=ISR0_IDX;
	pptr->dcd.irqmask=SAB82532_ISR0_CDSC;
	pptr->dcd.cnst = 0;
	
	pptr->cts.reg = (unsigned char *)&(STAR);
	pptr->cts.mask = SAB82532_STAR_CTS;
	pptr->cts.inverted = 0;
	pptr->cts.irq=ISR1_IDX;
	pptr->cts.irqmask=SAB82532_ISR1_CSC;
	pptr->cts.cnst = 0;
	
	pptr->rts.reg = (unsigned char *)&(MODE);
	pptr->rts.mask = SAB82532_MODE_FRTS;
	pptr->rts.inverted = 1;
	pptr->rts.cnst = SAB82532_MODE_RTS;
	
	
	/* Set the read and write function */
	pptr->readbyte=aura_readb;
	pptr->readword=aura_readw;
	pptr->writebyte=aura_writeb;
	pptr->writeword=aura_writew;
	pptr->readfifo=aura_readfifo;
	pptr->writefifo=aura_writefifo;
	
	sab8253x_setup_ttyport(pptr);	/* asynchronous */
	/* ttys are default, basic */
	/* initialization, everything */
	/* else works as a modification */
	/* thereof */
	
	pptr->next = AuraPortRoot;
	AuraPortRoot = pptr;
	pptr->next_by_chip = cptr->c_portbase;
	cptr->c_portbase = pptr;
	pptr->next_by_board = bptr->board_portbase;
	bptr->board_portbase = pptr;
}

/* Multichannel server functions */

static SAB_CHIP* CreateESCC8fromCIM(SAB_BOARD *bptr, AURA_CIM *cim, unsigned int chipno)
{
	SAB_CHIP *cptr;
	unsigned int regbase;
	
	printk(KERN_ALERT 
	       "auraXX20n: creating ESCC8 %d structure on board %p from cim %p.\n",
	       chipno, bptr, cim);
	
	cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL);
	if(cptr == NULL)
	{
		printk(KERN_ALERT
		       "auraXX20n: Failed to create ESCC8 structure %d on board %p at from cim %p.\n",
		       chipno, bptr, cim);
		return NULL;
	}
	
	memset(cptr, 0, sizeof(SAB_CHIP));
	cptr->chip_type = ESCC8;
	cptr->c_board = bptr;
	cptr->c_cim = cim;
	cptr->c_chipno = chipno;
	cptr->c_revision = 
		(readb((unsigned char *) (bptr->CIMCMD_REG +
					  (CIMCMD_RDREGB | (((chipno*8) << 6) | SAB85232_REG_VSTR))))
		 & SAB82532_VSTR_VN_MASK);
	cptr->c_nports = 8;
	cptr->c_portbase = NULL;	/* used for the list of ports associated
					   with this chip
					*/
	cptr->next = AuraChipRoot;
	AuraChipRoot = cptr;
	cptr->next_by_board = bptr->board_chipbase;
	bptr->board_chipbase = cptr;
	
	cptr->next_by_cim = cim->ci_chipbase;
	cim->ci_chipbase = cptr;
	
	printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n",
	       cptr->c_chipno, bptr, cptr->c_revision);
	
	/* lets set up the generic parallel
	 * port register which is used to
	 * control signaling and other stuff*/
	
	/* SAB82538 4 8-bits parallel ports
	 * To summarize the use of the parallel port:
	 *                    RS-232
	 * Parallel port A -- TxClkdir control	(output) ports 0 - 7
	 * Parallel port B -- DTR		(output) ports 0 - 7
	 * Parallel port C -- DSR		(input)  ports 0 - 7
	 * Parallel port D -- driver power down 	(output) drivers 0 - 3
	 *
	 * Note port D is not used on recent boards
	 */
	
	regbase = (unsigned int)
		(bptr->CIMCMD_REG + (0 | (((chipno*8) << 6) | 0)));	/* need to add in RDB/WRB cmd bits
									 * and reg offset (> 32) */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port A (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_A, SAB82538_REG_PIM_A, SAB82538_REG_PVR_A));
	
	/* Configuring Parallel Port A  (Clkdir)*/
	writeb(0x00,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_A));  /* All output bits */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_A)); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PVR_A));  /* All low */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port B (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_B,SAB82538_REG_PIM_B,SAB82538_REG_PVR_B));
	
	writeb(0x00,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_B));  /* All output bits */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_B)); /* All interrupts off */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PVR_B));  /* All low */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port C (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_C, SAB82538_REG_PIM_C, SAB82538_REG_PVR_C));
	
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_C));  /* All intput bits */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_C)); /* All interrupts off */
	/* don't set port value register on input register */
	
	/* Configuring Parallel Port D */
	
	DEBUGPRINT((KERN_ALERT "Setting up parallel port D (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
		    SAB82538_REG_PCR_D, SAB82538_REG_PIM_D, SAB82538_REG_PVR_D));
	writeb(0x0f,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_D));  /* 4 input  bits */
	writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_D)); /* All interrupts off */
	/* don't set port value register on input register */
	
	/* The priority rotation thing */
	
	DEBUGPRINT((KERN_ALERT "Setting IVA (0x%x +  0x%x = 0x%x\n", regbase,
		    SAB82532_REG_IVA, regbase + SAB82532_REG_IVA));
	
	writeb(SAB82538_IVA_ROT, ((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82532_REG_IVA)); 
	writeb(0, ((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82532_REG_IPC)); 
	
	cptr->c_regs = (void*) regbase;
	cptr->int_disable = DisableESCC8InterruptsFromCIM;
	return cptr;
}

static void CreateESCC8PortWithCIM(SAB_CHIP *cptr, unsigned int portno, 
				   AURA_CIM *cim, unsigned flag)
{
	SAB_BOARD *bptr;
	SAB_PORT  *pptr;
	extern void sab8253x_setup_ttyport(struct sab_port *p_port) ;
	
	++NumSab8253xPorts;
	bptr = cptr->c_board;
	pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL);
	if(pptr == NULL)
	{
		printk(KERN_ALERT
		       "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n",
		       cptr, bptr);
		return;
	}
	memset(pptr, 0, sizeof(SAB_PORT));
	DEBUGPRINT
		((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n", 
		  portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number));
	pptr->portno = portno;
	pptr->chip=cptr;
	pptr->board=bptr;
	pptr->open_type=OPEN_NOT;
	pptr->is_console=0;
	pptr->regs=
		(union sab82532_regs *)
		(((unsigned int)cptr->c_regs) +
		 (portno << 6));		/* addressing is different when there is a cim */
	pptr->type = cptr->c_revision;
	pptr->function = (((cim->ci_flags & CIM_SYNC) || flag) ? FUNCTION_NR : 
			  FUNCTION_AO);
	
	pptr->irq = bptr->b_irq;
	
	pptr->dsr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_C; 
	pptr->dsr.mask = 0x1 << portno;
	pptr->dsr.inverted = 1;
	pptr->dsr.irq=PIS_IDX;	/* need to check this constant */
	pptr->dsr.irqmask=0x1 << portno;
	pptr->dsr.cnst = 0;
	
	pptr->txclkdir.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_A;
	pptr->txclkdir.mask = 0x1 << portno;
	/* NOTE: Early 8 ports  boards had different tx clkdir sense */
	pptr->txclkdir.inverted = 1;
	
	pptr->dtr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_B;
	pptr->dtr.mask = 0x1 << portno;
	pptr->dtr.inverted = 1;
	pptr->dtr.cnst = 0;
	
	pptr->dcd.reg = ((unsigned char *)pptr->regs) + SAB85232_REG_VSTR;
	
	DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr->dcd.reg));
	
	pptr->dcd.mask = SAB82532_VSTR_CD;
	pptr->dcd.inverted = 1;
	pptr->dcd.irq=ISR0_IDX;
	pptr->dcd.irqmask=SAB82532_ISR0_CDSC;
	pptr->dcd.cnst = 0;
	
	pptr->cts.reg = (unsigned char *)&(STAR);
	pptr->cts.mask = SAB82532_STAR_CTS;
	pptr->cts.inverted = 0;
	pptr->cts.irq=ISR1_IDX;
	pptr->cts.irqmask=SAB82532_ISR1_CSC;
	pptr->cts.cnst = 0;
	
	pptr->rts.reg = (unsigned char *)&(MODE);
	pptr->rts.mask = SAB82532_MODE_FRTS;
	pptr->rts.inverted = 1;
	pptr->rts.cnst = SAB82532_MODE_RTS;
	
	
	/* Set the read and write function */
	pptr->readbyte=wmsaura_readb;
	pptr->readword=wmsaura_readw;
	pptr->writebyte=wmsaura_writeb;
	pptr->writeword=wmsaura_writew;
	pptr->readfifo=wmsaura_readfifo;
	pptr->writefifo=wmsaura_writefifo;
	
	sab8253x_setup_ttyport(pptr);	/* asynchronous */
	/* ttys are default, basic */
	/* initialization, everything */
	/* else works as a modification */
	/* thereof */
	
	pptr->next = AuraPortRoot;
	AuraPortRoot = pptr;
	
	pptr->next_by_chip = cptr->c_portbase;
	cptr->c_portbase = pptr;
	
	pptr->next_by_board = bptr->board_portbase;
	bptr->board_portbase = pptr;
	
	pptr->next_by_cim = cim->ci_portbase;
	cim->ci_portbase = pptr;
}

static void CreateCIMs(SAB_BOARD *bptr)
{
	unsigned int cimnum;
	unsigned char *wrcsr;
	unsigned char *rdcsr;
	unsigned char tmp;
	AURA_CIM *cim;
	unsigned short intrmask;