hpt366.c

一个2.4.21版本的嵌入式linux内核

			if (hpt_minimum_revision(dev,8))
				pci_set_drvdata(dev, NULL);
			else if (hpt_minimum_revision(dev,5))
				pci_set_drvdata(dev, (void *) fifty_base_hpt372);
			else if (hpt_minimum_revision(dev,4))
				pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
			else
				pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
			printk("HPT37X: using 50MHz PCI clock\n");
		} else {
			if (hpt_minimum_revision(dev,8))
			{
				printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
				pci_set_drvdata(dev, NULL);
			}
			else if (hpt_minimum_revision(dev,5))
				pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
			else if (hpt_minimum_revision(dev,4))
				pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
			else
				pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
			printk("HPT37X: using 66MHz PCI clock\n");
		}
	}
			
	/*
	 * only try the pll if we don't have a table for the clock
	 * speed that we're running at. NOTE: the internal PLL will
	 * result in slow reads when using a 33MHz PCI clock. we also
	 * don't like to use the PLL because it will cause glitches
	 * on PRST/SRST when the HPT state engine gets reset.
	 *
	 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
	 * 372 device so we can get ATA133 support
	 */
	if (pci_get_drvdata(dev)) 
		goto init_hpt37X_done;
	
	/*
	 * adjust PLL based upon PCI clock, enable it, and wait for
	 * stabilization.
	 */
	adjust = 0;
	freq = (pll < F_LOW_PCI_50) ? 2 : 4;
	while (adjust++ < 6) {
		pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
				       pll | 0x100);

		/* wait for clock stabilization */
		for (i = 0; i < 0x50000; i++) {
			pci_read_config_byte(dev, 0x5b, &reg5bh);
			if (reg5bh & 0x80) {
				/* spin looking for the clock to destabilize */
				for (i = 0; i < 0x1000; ++i) {
					pci_read_config_byte(dev, 0x5b, 
							     &reg5bh);
					if ((reg5bh & 0x80) == 0)
						goto pll_recal;
				}
				pci_read_config_dword(dev, 0x5c, &pll);
				pci_write_config_dword(dev, 0x5c, 
						       pll & ~0x100);
				pci_write_config_byte(dev, 0x5b, 0x21);
				if (hpt_minimum_revision(dev,8))
					return -EOPNOTSUPP;
				else if (hpt_minimum_revision(dev,5))
					pci_set_drvdata(dev, (void *) fifty_base_hpt372);
				else if (hpt_minimum_revision(dev,4))
					pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
				else
					pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
				printk("HPT37X: using 50MHz internal PLL\n");
				goto init_hpt37X_done;
			}
		}
pll_recal:
		if (adjust & 1)
			pll -= (adjust >> 1);
		else
			pll += (adjust >> 1);
	} 

init_hpt37X_done:
	/* reset state engine */
	pci_write_config_byte(dev, 0x50, 0x37); 
	pci_write_config_byte(dev, 0x54, 0x37); 
	udelay(100);
	return 0;
}

static int __init init_hpt366 (struct pci_dev *dev)
{
	u32 reg1	= 0;
	u8 drive_fast	= 0;

	/*
	 * Disable the "fast interrupt" prediction.
	 */
	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	pci_read_config_dword(dev, 0x40, &reg1);
									
	/* detect bus speed by looking at control reg timing: */
	switch((reg1 >> 8) & 7) {
		case 5:
			pci_set_drvdata(dev, (void *) forty_base_hpt366);
			break;
		case 9:
			pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
			break;
		case 7:
		default:
			pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
			break;
	}

	if (!pci_get_drvdata(dev))
	{
		printk(KERN_ERR "hpt366: unknown bus timing.\n");
		pci_set_drvdata(dev, NULL);
	}
	return 0;
}

static unsigned int __init init_chipset_hpt366 (struct pci_dev *dev, const char *name)
{
	int ret = 0;
	u8 test = 0;

	if (dev->resource[PCI_ROM_RESOURCE].start)
		pci_write_config_byte(dev, PCI_ROM_ADDRESS,
			dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);

	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
	if (test != (L1_CACHE_BYTES / 4))
		pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
			(L1_CACHE_BYTES / 4));

	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
	if (test != 0x78)
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);

	pci_read_config_byte(dev, PCI_MIN_GNT, &test);
	if (test != 0x08)
		pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);

	pci_read_config_byte(dev, PCI_MAX_LAT, &test);
	if (test != 0x08)
		pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	if (hpt_minimum_revision(dev, 3)) {
		ret = init_hpt37x(dev);
	} else {
		ret =init_hpt366(dev);
	}
	if (ret)
		return ret;
	
#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
	hpt_devs[n_hpt_devs++] = dev;

	if (!hpt366_proc) {
		hpt366_proc = 1;
		ide_pci_register_host_proc(&hpt366_procs[0]);
	}
#endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */

	return dev->irq;
}

static void __init init_hwif_hpt366 (ide_hwif_t *hwif)
{
	struct pci_dev *dev		= hwif->pci_dev;
	u8 ata66 = 0, regmask		= (hwif->channel) ? 0x01 : 0x02;
	u8 did, rid;
	unsigned long dmabase		= hwif->dma_base;
	int is_372n = 0;
	
	if(dmabase)
	{
		did = inb(dmabase + 0x22);
		rid = inb(dmabase + 0x28);
	
		if((did == 4 && rid == 6) || (did == 5 && rid > 1))
			is_372n = 1;
	}
		
	if(is_372n)
		printk(KERN_ERR "HPT372N support is EXPERIMENTAL ONLY.\n");
		
	hwif->tuneproc			= &hpt3xx_tune_drive;
	hwif->speedproc			= &hpt3xx_tune_chipset;
	hwif->quirkproc			= &hpt3xx_quirkproc;
	hwif->intrproc			= &hpt3xx_intrproc;
	hwif->maskproc			= &hpt3xx_maskproc;
	
	if(is_372n)
		hwif->rw_disk = &hpt372n_rw_disk;

	/*
	 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
	 * address lines to access an external eeprom.  To read valid
	 * cable detect state the pins must be enabled as inputs.
	 */
	if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
		/*
		 * HPT374 PCI function 1
		 * - set bit 15 of reg 0x52 to enable TCBLID as input
		 * - set bit 15 of reg 0x56 to enable FCBLID as input
		 */
		u16 mcr3, mcr6;
		pci_read_config_word(dev, 0x52, &mcr3);
		pci_read_config_word(dev, 0x56, &mcr6);
		pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
		pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
		/* now read cable id register */
		pci_read_config_byte(dev, 0x5a, &ata66);
		pci_write_config_word(dev, 0x52, mcr3);
		pci_write_config_word(dev, 0x56, mcr6);
	} else if (hpt_minimum_revision(dev, 3)) {
		/*
		 * HPT370/372 and 374 pcifn 0
		 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
		 */
		u8 scr2;
		pci_read_config_byte(dev, 0x5b, &scr2);
		pci_write_config_byte(dev, 0x5b, scr2 & ~1);
		/* now read cable id register */
		pci_read_config_byte(dev, 0x5a, &ata66);
		pci_write_config_byte(dev, 0x5b, scr2);
	} else {
		pci_read_config_byte(dev, 0x5a, &ata66);
	}

#ifdef DEBUG
	printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
		ata66, (ata66 & regmask) ? "33" : "66",
		PCI_FUNC(hwif->pci_dev->devfn));
#endif /* DEBUG */

#ifdef HPT_SERIALIZE_IO
	/* serialize access to this device */
	if (hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;
#endif

	if (hpt_minimum_revision(dev,3)) {
		u8 reg5ah = 0;
			pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
		/*
		 * set up ioctl for power status.
		 * note: power affects both
		 * drives on each channel
		 */
		hwif->resetproc	= &hpt3xx_reset;
		hwif->busproc	= &hpt370_busproc;
//		hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
	} else if (hpt_minimum_revision(dev,2)) {
		hwif->resetproc	= &hpt3xx_reset;
		hwif->busproc	= &hpt3xx_tristate;
	} else {
		hwif->resetproc = &hpt3xx_reset;
		hwif->busproc   = &hpt3xx_tristate;
	}

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = 1;
		hwif->drives[1].autotune = 1;
		return;
	}

	hwif->ultra_mask = 0x7f;
	hwif->mwdma_mask = 0x07;

	if (!(hwif->udma_four))
		hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
	hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;

	if (hpt_minimum_revision(dev,8))
		hwif->ide_dma_end = &hpt374_ide_dma_end;
	else if (hpt_minimum_revision(dev,5))
		hwif->ide_dma_end = &hpt374_ide_dma_end;
	else if (hpt_minimum_revision(dev,3)) {
		hwif->ide_dma_begin = &hpt370_ide_dma_begin;
		hwif->ide_dma_end = &hpt370_ide_dma_end;
		hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
		hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
	} else if (hpt_minimum_revision(dev,2))
		hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
	else
		hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static void __init init_dma_hpt366 (ide_hwif_t *hwif, unsigned long dmabase)
{
	u8 masterdma	= 0, slavedma = 0;
	u8 dma_new	= 0, dma_old = 0;
	u8 primary	= hwif->channel ? 0x4b : 0x43;
	u8 secondary	= hwif->channel ? 0x4f : 0x47;
	unsigned long flags;

	if (!dmabase)
		return;
		
	if(pci_get_drvdata(hwif->pci_dev) == NULL)
	{
		printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
		return;
	}

	dma_old = hwif->INB(dmabase+2);

	local_irq_save(flags);

	dma_new = dma_old;
	pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
	pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);

	if (masterdma & 0x30)	dma_new |= 0x20;
	if (slavedma & 0x30)	dma_new |= 0x40;
	if (dma_new != dma_old)
		hwif->OUTB(dma_new, dmabase+2);

	local_irq_restore(flags);

	ide_setup_dma(hwif, dmabase, 8);
}

extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
extern void ide_setup_pci_devices(struct pci_dev *, struct pci_dev *, ide_pci_device_t *);

static void __init init_setup_hpt374 (struct pci_dev *dev, ide_pci_device_t *d)
{
	struct pci_dev *findev = NULL;

	if (PCI_FUNC(dev->devfn) & 1)
		return;

	pci_for_each_dev(findev) {
		if ((findev->vendor == dev->vendor) &&
		    (findev->device == dev->device) &&
		    ((findev->devfn - dev->devfn) == 1) &&
		    (PCI_FUNC(findev->devfn) & 1)) {
			u8 irq = 0, irq2 = 0;
			pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
			pci_read_config_byte(findev, PCI_INTERRUPT_LINE, &irq2);
			if (irq != irq2) {
				pci_write_config_byte(findev,
						PCI_INTERRUPT_LINE, irq);
				findev->irq = dev->irq;
				printk("%s: pci-config space interrupt "
					"fixed.\n", d->name);
			}
			ide_setup_pci_devices(dev, findev, d);
			return;
		}
	}
	ide_setup_pci_device(dev, d);
}

static void __init init_setup_hpt37x (struct pci_dev *dev, ide_pci_device_t *d)
{
	ide_setup_pci_device(dev, d);
}

static void __init init_setup_hpt366 (struct pci_dev *dev, ide_pci_device_t *d)
{
	struct pci_dev *findev = NULL;
	u8 pin1 = 0, pin2 = 0;
	unsigned int class_rev;
	char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
				 "HPT370", "HPT370A", "HPT372"};

	if (PCI_FUNC(dev->devfn) & 1)
		return;

	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xff;

	/* New ident 372N reports revision 1. We could do the 
	   io port based type identification instead perhaps (DID, RID) */
	   
	if(d->device == PCI_DEVICE_ID_TTI_HPT372N)
		class_rev = 5;
		
	strcpy(d->name, chipset_names[class_rev]);

	switch(class_rev) {
		case 5:
		case 4:
		case 3: ide_setup_pci_device(dev, d);
			return;
		default:	break;
	}

	d->channels = 1;

	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
	pci_for_each_dev(findev) {
		if ((findev->vendor == dev->vendor) &&
		    (findev->device == dev->device) &&
		    ((findev->devfn - dev->devfn) == 1) &&
		    (PCI_FUNC(findev->devfn) & 1)) {
			pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
			if ((pin1 != pin2) && (dev->irq == findev->irq)) {
				d->bootable = ON_BOARD;
				printk("%s: onboard version of chipset, "
					"pin1=%d pin2=%d\n", d->name,
					pin1, pin2);
			}
			ide_setup_pci_devices(dev, findev, d);
			return;
		}
	}
	ide_setup_pci_device(dev, d);
}


/**
 *	hpt366_init_one	-	called when an HPT366 is found
 *	@dev: the hpt366 device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];

	if (dev->device != d->device)
		BUG();
	d->init_setup(dev, d);
	MOD_INC_USE_COUNT;
	return 0;
}

static struct pci_device_id hpt366_pci_tbl[] __devinitdata = {
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	{ PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
	{ 0, },
};

static struct pci_driver driver = {
	.name		= "HPT366 IDE",
	.id_table	= hpt366_pci_tbl,
	.probe		= hpt366_init_one,
};

static int hpt366_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

static void hpt366_ide_exit(void)
{
	ide_pci_unregister_driver(&driver);
}

module_init(hpt366_ide_init);
module_exit(hpt366_ide_exit);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
MODULE_LICENSE("GPL");

EXPORT_NO_SYMBOLS;