pcibr_intr.c

一个2.4.21版本的嵌入式linux内核

            void                   *int_addr;

	    /* if the interrupt line is now shared,
	     * do not disconnect it.
	     */
	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
		continue;

	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;

	    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev,
			"pcibr_intr_disconnect: disconnect int_bits=0x%x\n",
			pcibr_int_bits));

	    /* if we are sharing the interrupt line,
	     * connect us up; this closes the hole
	     * where the another pcibr_intr_alloc()
	     * was in progress as we disconnected.
	     */
	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
		continue;

	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
            if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
                continue;

            if (IS_PIC_SOFT(pcibr_soft))
                int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
            else
                int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr);

	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
				pcibr_intr_func, (intr_arg_t) intr_wrap,
			       (xtalk_intr_setfunc_t)pcibr_setpciint,
			       (void *)pcibr_int_bit);
	    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev,
			"pcibr_intr_disconnect: now-sharing int_bits=0x%x\n",
			pcibr_int_bit));
	}
}

/*ARGSUSED */
devfs_handle_t
pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
{
    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
    unsigned                pcibr_int_bit;

    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
	if (pcibr_int_bits & (1 << pcibr_int_bit))
	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
    return 0;
}

/* =====================================================================
 *    INTERRUPT HANDLING
 */
void
pcibr_clearwidint(bridge_t *bridge)
{
    bridge->b_wid_int_upper = 0;
    bridge->b_wid_int_lower = 0;
}


void
pcibr_setwidint(xtalk_intr_t intr)
{
    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
    iopaddr_t               addr = xtalk_intr_addr_get(intr);
    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;

    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);

    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
			       XTALK_ADDR_TO_UPPER(addr));
    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);

    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
    OLD_b_wid_int_lower = bridge->b_wid_int_lower;

    /* Verify that all interrupts from this Bridge are using a single PI */
    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
	/*
	 * Once set, these registers shouldn't change; they should
	 * be set multiple times with the same values.
	 *
	 * If we're attempting to change these registers, it means
	 * that our heuristics for allocating interrupts in a way
	 * appropriate for IP35 have failed, and the admin needs to
	 * explicitly direct some interrupts (or we need to make the
	 * heuristics more clever).
	 *
	 * In practice, we hope this doesn't happen very often, if
	 * at all.
	 */
	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
	}
    }

    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
    bridge->b_int_host_err = vect;

printk("pcibr_setwidint: b_wid_int_upper 0x%x b_wid_int_lower 0x%x b_int_host_err 0x%x\n",
	NEW_b_wid_int_upper, NEW_b_wid_int_lower, vect);

}

/*
 * pcibr_intr_preset: called during mlreset time
 * if the platform specific code needs to route
 * one of the Bridge's xtalk interrupts before the
 * xtalk infrastructure is available.
 */
void
pcibr_xintr_preset(void *which_widget,
		   int which_widget_intr,
		   xwidgetnum_t targ,
		   iopaddr_t addr,
		   xtalk_intr_vector_t vect)
{
    bridge_t               *bridge = (bridge_t *) which_widget;

    if (which_widget_intr == -1) {
	/* bridge widget error interrupt */
	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
				   XTALK_ADDR_TO_UPPER(addr));
	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
	bridge->b_int_host_err = vect;
printk("pcibr_xintr_preset: b_wid_int_upper 0x%lx b_wid_int_lower 0x%lx b_int_host_err 0x%x\n",
	( (0x000F0000 & (targ << 16)) | XTALK_ADDR_TO_UPPER(addr)),
	XTALK_ADDR_TO_LOWER(addr), vect);

	/* turn on all interrupts except
	 * the PCI interrupt requests,
	 * at least at heart.
	 */
	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;

    } else {
	/* routing a PCI device interrupt.
	 * targ and low 38 bits of addr must
	 * be the same as the already set
	 * value for the widget error interrupt.
	 */
	bridge->b_int_addr[which_widget_intr].addr =
	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
	     (BRIDGE_INT_ADDR_FLD & vect));
	/*
	 * now bridge can let it through;
	 * NB: still should be blocked at
	 * xtalk provider end, until the service
	 * function is set.
	 */
	bridge->b_int_enable |= 1 << vect;
    }
    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
}


/*
 * pcibr_intr_func()
 *
 * This is the pcibr interrupt "wrapper" function that is called,
 * in interrupt context, to initiate the interrupt handler(s) registered
 * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
 * handlers will be called directly, and threaded handlers will have their 
 * thread woken up.
 */
void
pcibr_intr_func(intr_arg_t arg)
{
    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
    reg_p                   wrbf;
    intr_func_t             func;
    pcibr_intr_t            intr;
    pcibr_intr_list_t       list;
    int                     clearit;
    int			    do_nonthreaded = 1;
    int			    is_threaded = 0;
    int			    x = 0;
    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
    bridge_t               *bridge = pcibr_soft->bs_base;
    uint64_t		    p_enable = pcibr_soft->bs_int_enable;
    int			    bit = wrap->iw_ibit;

	/*
	 * PIC WAR.  PV#855272
	 * Early attempt at a workaround for the runaway
	 * interrupt problem.   Briefly disable the enable bit for
	 * this device.
	 */
	if (IS_PIC_SOFT(pcibr_soft) &&
			PCIBR_WAR_ENABLED(PV855272, pcibr_soft)) {
		unsigned s;

		/* disable-enable interrupts for this bridge pin */

		p_enable &= ~(1 << bit);
	        s = pcibr_lock(pcibr_soft);
		bridge->p_int_enable_64 = p_enable;
		p_enable |= (1 << bit);
		bridge->p_int_enable_64 = p_enable;
	        pcibr_unlock(pcibr_soft, s);
	}

	/*
	 * If any handler is still running from a previous interrupt
	 * just return. If there's a need to call the handler(s) again,
	 * another interrupt will be generated either by the device or by
	 * pcibr_force_interrupt().
	 */

	if (wrap->iw_hdlrcnt) {
		return;
	}

    /*
     * Call all interrupt handlers registered.
     * First, the pcibr_intrd threads for any threaded handlers will be
     * awoken, then any non-threaded handlers will be called sequentially.
     */
	
	clearit = 1;
	while (do_nonthreaded) {
	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
		if ((intr = list->il_intr) && (intr->bi_flags & PCIIO_INTR_CONNECTED)) {

		    /*
		     * This device may have initiated write
		     * requests since the bridge last saw
		     * an edge on this interrupt input; flushing
		     * the buffer prior to invoking the handler
		     * should help but may not be sufficient if we 
		     * get more requests after the flush, followed
		     * by the card deciding it wants service, before
		     * the interrupt handler checks to see if things need
		     * to be done.
		     *
		     * There is a similar race condition if
		     * an interrupt handler loops around and
		     * notices further service is required.
		     * Perhaps we need to have an explicit
		     * call that interrupt handlers need to
		     * do between noticing that DMA to memory
		     * has completed, but before observing the
		     * contents of memory?
		     */

		    if ((do_nonthreaded) && (!is_threaded)) {
			/* Non-threaded -  Call the interrupt handler at interrupt level */
			/* Only need to flush write buffers if sharing */

			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
			    if ((x = *wrbf))	/* write request buffer flush */
#ifdef SUPPORT_PRINTING_V_FORMAT
				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
				    "write buffer flush failed, wrbf=0x%x\n", 
				    list->il_intr->bi_dev, wrbf);
#else
				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
				    "write buffer flush failed, wrbf=0x%lx\n", 
				    (void *)list->il_intr->bi_dev, (long) wrbf);
#endif
			}
			func = intr->bi_func;
			if ( func )
				func(intr->bi_arg);
		    }
		    clearit = 0;
		}
	    }
	    do_nonthreaded = 0;

	    /*
	     * If the non-threaded handler was the last to complete,
	     * (i.e., no threaded handlers still running) force an
	     * interrupt to avoid a potential deadlock situation.
	     */
	    if (wrap->iw_hdlrcnt == 0) {
		pcibr_force_interrupt(wrap);
	    }
	}

	/* If there were no handlers,
	 * disable the interrupt and return.
	 * It will get enabled again after
	 * a handler is connected.
	 * If we don't do this, we would
	 * sit here and spin through the
	 * list forever.
	 */
	if (clearit) {
	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
	    bridge_t               *bridge = pcibr_soft->bs_base;
	    bridgereg_t             int_enable;
	    bridgereg_t		    mask = 1 << wrap->iw_ibit;
	    unsigned long           s;

	    /* PIC BRINUGP WAR (PV# 854697):
	     * On PIC we must write 64-bit MMRs with 64-bit stores
	     */
	    s = pcibr_lock(pcibr_soft);
	    if (IS_PIC_SOFT(pcibr_soft) &&
				PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
		int_enable = bridge->p_int_enable_64;
		int_enable &= ~mask;
		bridge->p_int_enable_64 = int_enable;
	    } else {
		int_enable = (uint64_t)bridge->b_int_enable;
		int_enable &= ~mask;
		bridge->b_int_enable = (bridgereg_t)int_enable;
	    }
	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
	    pcibr_unlock(pcibr_soft, s);
	    return;
	}
}