gt64240.h

一个2.4.21版本的嵌入式linux内核

#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                      0x1ec4
#define PCI_1ACCESS_CONTROL_TOP_4                            0x1ec8
#define PCI_1ACCESS_CONTROL_BASE_5_LOW                       0c1ed0
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                      0x1ed4
#define PCI_1ACCESS_CONTROL_TOP_5                            0x1ed8
#define PCI_1ACCESS_CONTROL_BASE_6_LOW                       0c1ee0
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                      0x1ee4
#define PCI_1ACCESS_CONTROL_TOP_6                            0x1ee8
#define PCI_1ACCESS_CONTROL_BASE_7_LOW                       0c1ef0
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                      0x1ef4
#define PCI_1ACCESS_CONTROL_TOP_7                            0x1ef8

/****************************************/
/* PCI Snoop Control                    */
/****************************************/

#define PCI_0SNOOP_CONTROL_BASE_0_LOW                        0x1f00
#define PCI_0SNOOP_CONTROL_BASE_0_HIGH                       0x1f04
#define PCI_0SNOOP_CONTROL_TOP_0                             0x1f08
#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW                      0x1f10
#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f14
#define PCI_0SNOOP_CONTROL_TOP_1                             0x1f18
#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW                      0x1f20
#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH                     0x1f24
#define PCI_0SNOOP_CONTROL_TOP_2                             0x1f28
#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW                      0x1f30
#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH                     0x1f34
#define PCI_0SNOOP_CONTROL_TOP_3                             0x1f38
#define PCI_1SNOOP_CONTROL_BASE_0_LOW                        0x1f80
#define PCI_1SNOOP_CONTROL_BASE_0_HIGH                       0x1f84
#define PCI_1SNOOP_CONTROL_TOP_0                             0x1f88
#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW                      0x1f90
#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f94
#define PCI_1SNOOP_CONTROL_TOP_1                             0x1f98
#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW                      0x1fa0
#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH                     0x1fa4
#define PCI_1SNOOP_CONTROL_TOP_2                             0x1fa8
#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW                      0x1fb0
#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH                     0x1fb4
#define PCI_1SNOOP_CONTROL_TOP_3                             0x1fb8

/****************************************/
/* PCI Configuration Address            */
/****************************************/

#define PCI_0CONFIGURATION_ADDRESS 				0xcf8
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xcfc
#define PCI_1CONFIGURATION_ADDRESS 				0xc78
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xc7c
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xc34
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xcb4

/****************************************/
/* PCI Error Report                     */
/****************************************/

#define PCI_0SERR_MASK						 0xc28
#define PCI_0ERROR_ADDRESS_LOW                               0x1d40
#define PCI_0ERROR_ADDRESS_HIGH                              0x1d44
#define PCI_0ERROR_DATA_LOW                                  0x1d48
#define PCI_0ERROR_DATA_HIGH                                 0x1d4c
#define PCI_0ERROR_COMMAND                                   0x1d50
#define PCI_0ERROR_CAUSE                                     0x1d58
#define PCI_0ERROR_MASK                                      0x1d5c

#define PCI_1SERR_MASK						 0xca8
#define PCI_1ERROR_ADDRESS_LOW                               0x1dc0
#define PCI_1ERROR_ADDRESS_HIGH                              0x1dc4
#define PCI_1ERROR_DATA_LOW                                  0x1dc8
#define PCI_1ERROR_DATA_HIGH                                 0x1dcc
#define PCI_1ERROR_COMMAND                                   0x1dd0
#define PCI_1ERROR_CAUSE                                     0x1dd8
#define PCI_1ERROR_MASK                                      0x1ddc


/****************************************/
/* Lslave Debug  (for internal use)     */
/****************************************/

#define L_SLAVE_X0_ADDRESS                                  0x1d20
#define L_SLAVE_X0_COMMAND_AND_ID                           0x1d24
#define L_SLAVE_X1_ADDRESS                                  0x1d28
#define L_SLAVE_X1_COMMAND_AND_ID                           0x1d2c
#define L_SLAVE_WRITE_DATA_LOW                              0x1d30
#define L_SLAVE_WRITE_DATA_HIGH                             0x1d34
#define L_SLAVE_WRITE_BYTE_ENABLE                           0x1d60
#define L_SLAVE_READ_DATA_LOW                               0x1d38
#define L_SLAVE_READ_DATA_HIGH                              0x1d3c
#define L_SLAVE_READ_ID                                     0x1d64

/****************************************/
/* PCI Configuration Function 0         */
/****************************************/

#define PCI_DEVICE_AND_VENDOR_ID 				0x000
#define PCI_STATUS_AND_COMMAND					0x004
#define PCI_CLASS_CODE_AND_REVISION_ID			        0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 		0x00C
#define PCI_SCS_0_BASE_ADDRESS	    				0x010
#define PCI_SCS_1_BASE_ADDRESS 					0x014
#define PCI_SCS_2_BASE_ADDRESS 					0x018
#define PCI_SCS_3_BASE_ADDRESS      				0x01C
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID		0x02C
#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER			0x030
#define PCI_CAPABILTY_LIST_POINTER                          0x034
#define PCI_INTERRUPT_PIN_AND_LINE 			    0x03C
#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
#define PCI_VPD_ADDRESS                                     0x048
#define PCI_VPD_DATA                                        0X04c
#define PCI_MSI_MESSAGE_CONTROL                             0x050
#define PCI_MSI_MESSAGE_ADDRESS                             0x054
#define PCI_MSI_MESSAGE_UPPER_ADDRESS                       0x058
#define PCI_MSI_MESSAGE_DATA                                0x05c
#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                 0x058

/****************************************/
/* PCI Configuration Function 1         */
/****************************************/

#define PCI_CS_0_BASE_ADDRESS	    				0x110
#define PCI_CS_1_BASE_ADDRESS 					0x114
#define PCI_CS_2_BASE_ADDRESS 					0x118
#define PCI_CS_3_BASE_ADDRESS     				0x11c
#define PCI_BOOTCS_BASE_ADDRESS                     	    0x120

/****************************************/
/* PCI Configuration Function 2         */
/****************************************/

#define PCI_P2P_MEM0_BASE_ADDRESS	    			0x210
#define PCI_P2P_MEM1_BASE_ADDRESS 				0x214
#define PCI_P2P_I_O_BASE_ADDRESS 				0x218
#define PCI_CPU_BASE_ADDRESS      				0x21c

/****************************************/
/* PCI Configuration Function 4         */
/****************************************/

#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 				0x410
#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH			 	0x414
#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW   			0x418
#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH  		    0x41c
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW              	    0x420
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH             	    0x424


/****************************************/
/* PCI Configuration Function 5         */
/****************************************/

#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 				0x510
#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH				0x514
#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW   		 	0x518
#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH  		 	0x51c
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW              	    0x520
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH             	    0x524


/****************************************/
/* PCI Configuration Function 6         */
/****************************************/

#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 				0x610
#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH				0x614
#define PCI_DAC_CS_1_BASE_ADDRESS_LOW   			0x618
#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH  			0x61c
#define PCI_DAC_CS_2_BASE_ADDRESS_LOW            	        0x620
#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH           	        0x624

/****************************************/
/* PCI Configuration Function 7         */
/****************************************/

#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 				0x710
#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH			 	0x714
#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW   		 	0x718
#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH  			0x71c
#define PCI_DAC_CPU_BASE_ADDRESS_LOW            	        0x720
#define PCI_DAC_CPU_BASE_ADDRESS_HIGH           	        0x724

/****************************************/
/* Interrupts	  			*/
/****************************************/

#define LOW_INTERRUPT_CAUSE_REGISTER   				0xc18
#define HIGH_INTERRUPT_CAUSE_REGISTER				0xc68
#define CPU_INTERRUPT_MASK_REGISTER_LOW				0xc1c
#define CPU_INTERRUPT_MASK_REGISTER_HIGH			0xc6c
#define CPU_SELECT_CAUSE_REGISTER				0xc70
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xc24
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xc64
#define PCI_0SELECT_CAUSE                                   0xc74
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xca4
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xce4
#define PCI_1SELECT_CAUSE                                   0xcf4
#define CPU_INT_0_MASK                                      0xe60
#define CPU_INT_1_MASK                                      0xe64
#define CPU_INT_2_MASK                                      0xe68
#define CPU_INT_3_MASK                                      0xe6c

/****************************************/
/* I20 Support registers		*/
/****************************************/

#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE			0x010
#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE  			0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 			0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE  			0x01C
#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE  			0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE  		0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE		0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 			0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE   		0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE   		0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE  		0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE   	0x044
#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 			0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 			0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE		0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE  		0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 		0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 		0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE		0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE		0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE		0x0F8
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE		0x0FC

#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE				0x090
#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE  				0x094
#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 				0x098
#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE  				0x09C
#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE  				0x0A0
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE  		0x0A4
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE			0x0A8
#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 				0x0AC
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE   		0x0B0
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE   		0x0B4
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE  		0x0C0
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE   	0x0C4
#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 				0x0D0
#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 				0x0D4
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0E0
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE  		0x0E4
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 		0x0E8
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 		0x0EC
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0F0
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0F4
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE		0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE		0x07C

#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE				0X1C10
#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE  				0X1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 				0X1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE  				0X1C1C
#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE  				0X1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE  		0X1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE			0X1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 				0X1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE   		0X1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE   		0X1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE  		0X1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE   	0X1C44
#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 				0X1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 				0X1C54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE  		0X1C64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 		0X1C68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 		0X1C6C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1CF8
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1CFC

#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE				0X1C90
#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE  				0X1C94
#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 				0X1C98
#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE  				0X1C9C
#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE  				0X1CA0
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE  		0X1CA4
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE			0X1CA8
#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 				0X1CAC
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE   		0X1CB0
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE   		0X1CB4
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE  		0X1CC0
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE   	0X1CC4
#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 				0X1CD0
#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 				0X1CD4
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CE0
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE  		0X1CE4
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 		0X1CE8
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 		0X1CEC
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CF0
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CF4
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1C78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1C7C

/****************************************/
/* Communication Unit Registers         */
/****************************************/

#define ETHERNET_0_ADDRESS_CONTROL_LOW
#define ETHERNET_0_ADDRESS_CONTROL_HIGH                     0xf204
#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf208
#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf20c
#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf210
#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf214
#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS              0xf218