sbdreset_evb64120a.s

一个2.4.21版本的嵌入式linux内核

	sw  t0,0(v0)
        li  v0,0xb400041c
	li  t0,htoll(0x00)
	sw  t0,0(v0)

        /* Configure bank2 to 256 Mbit */
        DBG("Configure bank2 to 256 Mbit...\r\n")
        li  v0,0xb4000454
	li  t0,htoll(0x00004c69)
        sw  t0,0(v0)

        /* Config the SDRAM banks decode system */
	li  v0,0xb400047c
	li  t0,htoll(2)
	sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x3)
	sw  t0,0(v0)

        li  v0,0xa0000000
        li  t0,0
        sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x0)
	sw  t0,0(v0)

        /* Write to address 0x2000000 and check if 0x00000000 is being written too */
        DBG("Write to address 0x2000000 and check if 0x00000000 is being written too...\r\n")
        li  v0,0xa0000000
        li  t1,0xa0000010
        li  t0,htoll(0x0)
1:      sw  t0,0(v0)
        addu v0,4
        bne t1,v0,1b

        /* The address should activate Dadr12 */
        li  v0,0xa2000000
	li  t0,0x11111111
        sw  t0,0(v0)
        li  v0,0xa0000010
        li  t1,0xa0000100
        li  t0,0x22222222
2:      sw  t0,0(v0)
        addu v0,4
        bne t1,v0,2b

        DBG("Check address 0x00000000 for duplications...\r\n")
        li    t0,0xa0000000
        li    v0,0x11111111
        lw    t0,(t0)
        bne   t0,v0,_256MBIT2

        /* Write to address 0x1000 and check if 0x00000000 is being written too */
        DBG("Write to address 0x1000 and check if 0x00000000 is being written too...\r\n")
        li  v0,0xa0000000
        li  t1,0xa0000010
        li  t0,htoll(0x0)
1:      sw  t0,0(v0)
        addu v0,4
        bne t1,v0,1b

        /* The address should activate bank select1*/
        li  v0,0xa0001000
	li  t0,0x11111111
        sw  t0,0(v0)
        li  v0,0xa0000010
        li  t1,0xa0000100
        li  t0,0x22222222
2:      sw  t0,0(v0)
        addu v0,4
        bne t1,v0,2b

        DBG("Check address 0x00000000 for duplications...\r\n")
        li    t0,0xa0000000
        li    v0,0x11111111
        lw    t0,(t0)
        beq   t0,v0,_16MBIT2

        /* Write to address 0x8000000 and check if 0x00000000 is being written too */
        DBG("Write to address 0x8000000 and check if 0x00000000 is being written too...\r\n")
        li  v0,0xa0000000
        li  t1,0xa0000010
        li  t0,htoll(0x0)
1:      sw  t0,0(v0)
        addu v0,4
        bne t1,v0,1b

        /* The address should activate Dadr9 which on the column cycle is in active with 64 Mbit
           device */
        li  v0,0xa8000000
	li  t0,0x11111111
        sw  t0,0(v0)
        li  v0,0xa0000010
        li  t1,0xa0000100
        li  t0,0x22222222
2:      sw  t0,0(v0)
        addu v0,4
        bne t1,v0,2b

        DBG("Check address 0x00000000 for duplications...\r\n")
        li    t0,0xa0000000
        li    v0,0x11111111
        lw    t0,(t0)
        beq   t0,v0,_64MBIT2
        b     _128MBIT2

_16MBIT2:
        DBG("16 Mbit SDRAM detected...\r\n")
        /* In 16 Mbit SDRAM we must use 2 way bank interleaving!!! */
        li  v0,0xb4000814
	li  t0,htoll(16)
	sw  t0,0(v0)
        li  t1,htoll(0x00000449)
        b   _INIT_SDRAM

_64MBIT2:
        DBG("64 Mbit SDRAM detected...\r\n")
        /* In 64 Mbit SDRAM we must use 4 way bank interleaving!!! */
        li  v0,0xb4000814
	li  t0,htoll(64)
	sw  t0,0(v0)
        li  t1,htoll(0x00000c69)
        b   _INIT_SDRAM

_128MBIT2:
        DBG("128 Mbit SDRAM detected...\r\n")
        /* In 128 Mbit SDRAM we must use 4 way bank interleaving!!! */
        li  v0,0xb4000814
	li  t0,htoll(128)
	sw  t0,0(v0)
        li  t1,htoll(0x00000c69)
        b   _INIT_SDRAM

_256MBIT2:
        DBG("256 Mbit SDRAM detected...\r\n")
        /* In 256 Mbit SDRAM we must use 4 way bank interleaving!!! */
        li  v0,0xb4000814
	li  t0,htoll(256)
	sw  t0,0(v0)
        li  t1,htoll(0x00004c69)
        b   _INIT_SDRAM

_INIT_SDRAM:
        /* Restore defaults */
        DBG("Restoring defaults...\r\n")
        li  v0,0xb4000404
	li  t0,htoll(0x07)
	sw  t0,0(v0)
        li  v0,0xb4000408
	li  t0,htoll(0x08)
	sw  t0,0(v0)
        li  v0,0xb400040c
	li  t0,htoll(0x0f)
	sw  t0,0(v0)
        li  v0,0xb4000410
	li  t0,htoll(0x10)
	sw  t0,0(v0)
        li  v0,0xb4000414
	li  t0,htoll(0x17)
	sw  t0,0(v0)
        li  v0,0xb4000418
	li  t0,htoll(0x18)
	sw  t0,0(v0)
        li  v0,0xb400041c
	li  t0,htoll(0x1f)
	sw  t0,0(v0)
        li  v0,0xb4000010
	li  t0,htoll(0x07)
	sw  t0,0(v0)
        li  v0,0xb4000018
	li  t0,htoll(0x008)
	sw  t0,0(v0)
        li  v0,0xb4000020
	li  t0,htoll(0x0f)
	sw  t0,0(v0)

        li  v0,0xb400044c
        sw  t1,8(v0)  # Bank2
        sw  t1,12(v0) # Bank3

        li  v0,0xb4000474
	li  t0,htoll(0x3)
	sw  t0,0(v0)

        li  v0,0xa0000000
        li  t0,0
        sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x0)
	sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x3)
	sw  t0,0(v0)

        li  v0,0xa0800000
        li  t0,0
        sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x0)
	sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x3)
	sw  t0,0(v0)

        li  v0,0xa1000000
        li  t0,0
        sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x0)
	sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x3)
	sw  t0,0(v0)

        li  v0,0xa1800000
        li  t0,0
        sw  t0,0(v0)

        li  v0,0xb4000474
	li  t0,htoll(0x0)
	sw  t0,0(v0)

        /*********************************************************************/
        /************************* SDRAM initializing ************************/
        /******************************* END *********************************/

        li      p64011, PA_TO_KVA1(GT64011_BASE)

        li      t0,htoll(0x00000000)    /* RAS[1:0] low decode address */
        sw      t0,0x008(p64011)

        li      t0,htoll(0x00000007)    /* RAS[1:0] high decode address */
        sw      t0,0x010(p64011)

        li      t0,htoll(0x00000000)    /* RAS[0] Low decode address */
        sw      t0,0x400(p64011)

        li      t0,htoll(0x0000000f)    /* RAS[0] High decode address */
        sw      t0,0x404(p64011)

        li      t0,htoll(0x00000008)    /* RAS[3:2] low decode address */
        sw      t0,0x018(p64011)

        li      t0,htoll(0x0000000f)    /* RAS[3:2] high decode address */
        sw      t0,0x020(p64011)

        li      t0,htoll(0x0000000f)    /* RAS[1] Low Decode Address */
        sw      t0,0x408(p64011)

        li      t0,htoll(0x00000008)    /* RAS[1] High Decode Address */
        sw      t0,0x40c(p64011)

        li      t0,htoll(0x00000010)    /* RAS[2] Low Decode Address */
        sw      t0,0x410(p64011)

        li      t0,htoll(0x00000017)    /* RAS[2] High Decode Address */
        sw      t0,0x414(p64011)

        li      t0,htoll(0x00000018)    /* RAS[3] Low Decode Address */
        sw      t0,0x418(p64011)

        li      t0,htoll(0x0000001f)    /* RAS[3] High Decode Address <<<<<< 1*/
        sw      t0,0x41c(p64011)

#ifdef DBGSBD
#define DREG(str,rname) \
	DBG(str); \
	DBG(":\t") ;			\
	lw	a0,rname(p64011) ;	\
	HTOLL(a0,t0) ;			\
	jal	_dbghex ;		\
	DBG("\r\n")

	DBG("GT-64120 settings:\r\n")
        DREG("DRAMPAR_BANK0   (44c)",GT_DRAMPAR_BANK0)
        DREG("DRAMPAR_BANK1   (450)",GT_DRAMPAR_BANK1)
        DREG("DRAMPAR_BANK2   (454)",GT_DRAMPAR_BANK2)
        DREG("DRAMPAR_BANK3   (458)",GT_DRAMPAR_BANK3)
        DREG("PAS_RAS10LO     (008)",GT_PAS_RAS10LO)
        DREG("PAS_RAS10HI     (010)",GT_PAS_RAS10HI)
        DREG("PAS_RAS32LO     (018)",GT_PAS_RAS32LO)
        DREG("PAS_RAS32HI     (020)",GT_PAS_RAS32HI)
        DREG("DDAS_RAS0LO     (400)",GT_DDAS_RAS0LO)
        DREG("DDAS_RAS0HI     (404)",GT_DDAS_RAS0HI)
        DREG("DDAS_RAS1LO     (408)",GT_DDAS_RAS1LO)
        DREG("DDAS_RAS1HI     (40c)",GT_DDAS_RAS1HI)
        DREG("DDAS_RAS2LO     (410)",GT_DDAS_RAS2LO)
        DREG("DDAS_RAS2HI     (414)",GT_DDAS_RAS2HI)
        DREG("DDAS_RAS3LO     (418)",GT_DDAS_RAS3LO)
        DREG("DDAS_RAS3HI     (41c)",GT_DDAS_RAS3HI)
        DREG("GT_DRAM_CFG     (448)",GT_DRAM_CFG)
        DREG("GT_DEVPAR_BANK0 (45c)",GT_DEVPAR_BANK0)
        DREG("GT_DEVPAR_BANK1 (460)",GT_DEVPAR_BANK1)
        DREG("GT_DEVPAR_BANK2 (464)",GT_DEVPAR_BANK2)
        DREG("GT_DEVPAR_BANK3 (468)",GT_DEVPAR_BANK3)
        DREG("GT_IPCI_TOR     (c04)",GT_IPCI_TOR)
#endif

	/* we can now initialise the caches for a fast clear_mem */
	SBD_DISPLAY ('C','A','C','H',CHKPNT_CACH)
	DBG("init_cache\r\n")
//	jal	mips_init_cache

.noinit:

	/* initialise tlb */
	SBD_DISPLAY ('I','T','L','B', CHKPNT_ITLB)
	DBG("init_tlb\r\n")
//	bal	init_tlb

//	DBG("sbdreset completed\r\n")
//	move	ra,rasave
        j       GetExtendedMemorySize
        nop

END(sbdreset)

LEAF(_sbd_memfail)
	SBD_DISPLAY ('!','M','E','M',CHKPNT_0MEM)
1:	b	1b
	j	ra
END(_sbd_memfail)

	.rdata
RefreshBits:
	.word	htoll(GT_DRAMPAR_Refresh512)
	.word	htoll(GT_DRAMPAR_Refresh1024)
	.word	htoll(GT_DRAMPAR_Refresh2048)
	.word	htoll(GT_DRAMPAR_Refresh4096)
	.text

/* DRAM: */
#define GT_DRAM_CFG_INIT \
        GT_DRAM_CFG_RefIntCnt(160) | \
        GT_DRAM_CFG_StagRefOn | \
        GT_DRAM_CFG_ADSFunctDRAM | \
        GT_DRAM_CFG_DRAMLatchActive

/* serial port:  widest timings even 8 bit bus, latch enabled no parity */
#define GT_DEVPAR_SERIALINIT \
        GT_DEVPAR_TurnOff(7) | \
        GT_DEVPAR_AccToFirst(15) | \
        GT_DEVPAR_AccToNext(15) | \
        GT_DEVPAR_ADStoWr(7) | \
        GT_DEVPAR_WrActive(7) | \
        GT_DEVPAR_WrHigh(7) | \
        GT_DEVPAR_DevWidth8 | \
        GT_DEVPAR_DevLocEven | \
        GT_DEVPAR_LatchFunctTransparent | \
        GT_DEVPAR_ParityDisable | \
        GT_DEVPAR_Reserved

/* PCI: */
#define GT_IPCI_TOR_INIT \
        GT_IPCI_TOR_Timeout0(255) | \
        GT_IPCI_TOR_Timeout1(255) | \
        GT_IPCI_TOR_RetryCtr(0)

#define INIT(addr,val) \
        .word   addr, val
#define GTINIT(addr,val) \
        INIT(PHYS_TO_K1(GT64011_BASE+(addr)), htoll(val))

        .rdata
reginittab:

        /* disable ras1:0 and ras3:2 decodes */
        GTINIT(GT_PAS_RAS10LO,  GT_PAS_LOMASK_Low);
        GTINIT(GT_PAS_RAS10HI,  0);
        GTINIT(GT_PAS_RAS32LO,  GT_PAS_LOMASK_Low);
        GTINIT(GT_PAS_RAS32HI,  0);

        /* disable RAS[0123] */
        GTINIT(GT_DDAS_RAS0LO,  GT_DDAS_LOMASK_Low)
        GTINIT(GT_DDAS_RAS0HI,  0);
        GTINIT(GT_DDAS_RAS1LO,  GT_DDAS_LOMASK_Low)
        GTINIT(GT_DDAS_RAS1HI,  0);
        GTINIT(GT_DDAS_RAS2LO,  GT_DDAS_LOMASK_Low)
        GTINIT(GT_DDAS_RAS2HI,  0);
        GTINIT(GT_DDAS_RAS3LO,  GT_DDAS_LOMASK_Low)
        GTINIT(GT_DDAS_RAS3HI,  0);

        /* 0x45c, 0x460, 0x464, 0x468 */
	/*GTINIT(GT_DEVPAR_BANK0, GT_DEVPAR_SERIALINIT)*/
        GTINIT(GT_DEVPAR_BANK0, 0x3847de60)
        GTINIT(GT_DEVPAR_BANK1, 0x146fffff)
        GTINIT(GT_DEVPAR_BANK2, 0x144fffff)
        GTINIT(GT_DEVPAR_BANK3, 0x167fffff)

        GTINIT(GT_IPCI_TOR,     GT_IPCI_TOR_INIT)
        INIT(0,0)
        .text

        .globl sbddelay

LEAF(sbdberrenb)
	mfc0	v0,C0_SR
	li	t0,SR_DE
	bnez	a0,1f
	or	t1,v0,t0	# disable cache/parity errors (SR_DE = 1)
	b	2f
1:	not	t1,t0		# enable cache/parity errors (SR_DE = 0)
	and	t1,v0
2:	mtc0	t1,C0_SR
	and	v0,t0		# get old SR_DE bit
	xor	v0,t0		# and invert to make it an enable bit
	j	ra
END(sbdberrenb)


LEAF(sbdberrcnt)
	move	v0,zero
	j	ra
END(sbdberrcnt)

	.lcomm	wbfltmp,4

LEAF(wbflush)
//XLEAF(mips_wbflush)
	sync
	la	t0,wbfltmp
	or	t0,K1BASE
	lw	zero,0(t0)
	j	ra
END(wbflush)


LEAF(sbddelay)
	li	t1,CACHEUS
	and	t0,ra,0x20000000
	beqz	t0,1f
	li	t1,ROMUS
1:	mul	a0,t1
	subu	a0,15		# approx number of loops so far

	.set	noreorder
	.set	nomacro
	nop
2:	bgtz	a0,2b
	subu	a0,1
	.set	macro
	.set	reorder

	j	ra
END(sbddelay)

#include "meminit.S"


LEAF(mips_cycle)
	.set	noreorder
	.set	nomacro
1:	bgtz	a0,1b
	subu	a0,1
	.set	macro
	.set	reorder
	j	ra
END(mips_cycle)

LEAF(init_ns16550_chan_b)
	# enable 16550 fifo if it is there
        li      a0,NS16550_CHANB
        li	t0,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
	sb	t0,FIFO(a0)

	/* convert baud rate in a1 into register value */
        li	t2,NS16550_HZ/(16*115200)	# brtc = CLK/16/speed

	li	t0,CFCR_DLAB			# select brtc divisor
	sb	t0,CFCR(a0)
	sb	t2,DATA(a0)			# store divisor lsb
	srl	t2,8
	sb	t2,IER(a0)			# store divisor msb

	li	t0,CFCR_8BITS			# set 8N1 mode
	sb	t0,CFCR(a0)

	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS
  	sb	t0,MCR(a0)
 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!)
	sb	t0,IER(a0)

	move	v0,zero				# indicate success
	j	ra

END(init_ns16550_chan_b)

LEAF(init_ns16550_chan_a)
	# enable 16550 fifo if it is there
        li      a0,NS16550_CHANA
        li	t0,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
	sb	t0,FIFO(a0)

	/* convert baud rate in a1 into register value */
        li	t2,NS16550_HZ/(16*9600)		# brtc = CLK/16/speed

	li	t0,CFCR_DLAB			# select brtc divisor
	sb	t0,CFCR(a0)
	sb	t2,DATA(a0)			# store divisor lsb
	srl	t2,8
	sb	t2,IER(a0)			# store divisor msb

	li	t0,CFCR_8BITS			# set 8N1 mode
	sb	t0,CFCR(a0)

	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS
  	sb	t0,MCR(a0)
 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!)
	sb	t0,IER(a0)

	move	v0,zero				# indicate success
	j	ra

END(init_ns16550_chan_a)

#endif /* EVB64120A */