gprs_new.rpt

51单片机系统扩展超大容量存储器接口设计的cpld源码。

-- Equation name is 'A21', type is output 
 A21     = LCELL( _EQ014 $  GND);
  _EQ014 =  A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D5 & !WR~
         #  A21 &  _X006;
  _X006  = EXP( A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D5 & !WR~);

-- Node name is 'CS_A~' 
-- Equation name is 'CS_A~', location is LC115, type is output.
 CS_A~   = LCELL( _EQ015 $  VCC);
  _EQ015 = !A5 & !A6 &  A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23;

-- Node name is 'CS_B~' 
-- Equation name is 'CS_B~', location is LC121, type is output.
 CS_B~   = LCELL( _EQ016 $  VCC);
  _EQ016 =  A5 & !A6 &  A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23;

-- Node name is 'CS_C~' 
-- Equation name is 'CS_C~', location is LC123, type is output.
 CS_C~   = LCELL( _EQ017 $  VCC);
  _EQ017 = !A5 &  A6 &  A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23;

-- Node name is 'CS_D~' 
-- Equation name is 'CS_D~', location is LC120, type is output.
 CS_D~   = LCELL( _EQ018 $  VCC);
  _EQ018 =  A5 &  A6 &  A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23;

-- Node name is 'CS_FLASH1~' 
-- Equation name is 'CS_FLASH1~', location is LC013, type is output.
 CS_FLASH1~ = LCELL( _EQ019 $  VCC);
  _EQ019 = !A22 & !A23;

-- Node name is 'CS_FLASH2~' 
-- Equation name is 'CS_FLASH2~', location is LC014, type is output.
 CS_FLASH2~ = LCELL( _EQ020 $  VCC);
  _EQ020 =  A22 & !A23;

-- Node name is 'CS_LED' 
-- Equation name is 'CS_LED', location is LC008, type is output.
 CS_LED  = LCELL( _EQ021 $  GND);
  _EQ021 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !WR~;

-- Node name is 'CS_SRAM~' 
-- Equation name is 'CS_SRAM~', location is LC016, type is output.
 CS_SRAM~ = LCELL( _EQ022 $ !A23);
  _EQ022 =  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 &  A15 &  A23;

-- Node name is 'D0' 
-- Equation name is 'D0', location is LC064, type is bidir.
D0       = TRI(_LC064,  _LC051);
_LC064   = LCELL( RB_FLASH1~ $  GND);

-- Node name is 'D1' 
-- Equation name is 'D1', location is LC062, type is bidir.
D1       = TRI(_LC062,  _LC051);
_LC062   = LCELL( RB_FLASH2~ $  GND);

-- Node name is 'D2' 
-- Equation name is 'D2', location is LC061, type is bidir.
D2       = OPNDRN(_LC061);
_LC061   = LCELL( _EQ023 $  VCC);
  _EQ023 = !A5 &  A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !RD~;

-- Node name is 'D3' 
-- Equation name is 'D3', location is LC059, type is bidir.
D3       = OPNDRN(_LC059);
_LC059   = LCELL( _EQ024 $  VCC);
  _EQ024 = !A5 &  A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !RD~;

-- Node name is 'D4' 
-- Equation name is 'D4', location is LC057, type is bidir.
D4       = TRI(_LC057,  _LC051);
_LC057   = LCELL( INTA $  GND);

-- Node name is 'D5' 
-- Equation name is 'D5', location is LC056, type is bidir.
D5       = TRI(_LC056,  _LC051);
_LC056   = LCELL( INTB $  GND);

-- Node name is 'D6' 
-- Equation name is 'D6', location is LC054, type is bidir.
D6       = TRI(_LC054,  _LC051);
_LC054   = LCELL( INTC $  GND);

-- Node name is 'D7~1' 
-- Equation name is 'D7~1', location is LC051, type is buried.
-- synthesized logic cell 
_LC051   = LCELL( _EQ025 $  GND);
  _EQ025 = !A5 &  A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !RD~;

-- Node name is 'D7' 
-- Equation name is 'D7', location is LC053, type is bidir.
D7       = TRI(_LC053,  _LC051);
_LC053   = LCELL( INTD $  GND);

-- Node name is 'INTSEL' 
-- Equation name is 'INTSEL', location is LC011, type is output.
 INTSEL  = LCELL( GND $  VCC);

-- Node name is 'IRQ_16C554~' 
-- Equation name is 'IRQ_16C554~', location is LC126, type is output.
 IRQ_16C554~ = LCELL( _EQ026 $  GND);
  _EQ026 = !INTA & !INTB;

-- Node name is 'LED_D5' = '|74373:113|:12' 
-- Equation name is 'LED_D5', type is output 
 LED_D5  = LCELL( _EQ027 $  GND);
  _EQ027 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D0 & !WR~
         #  LED_D5 &  _X007;
  _X007  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D0 & !WR~);

-- Node name is 'LED_D6' = '|74373:113|:13' 
-- Equation name is 'LED_D6', type is output 
 LED_D6  = LCELL( _EQ028 $  GND);
  _EQ028 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D1 & !WR~
         #  LED_D6 &  _X008;
  _X008  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D1 & !WR~);

-- Node name is 'LED_D7' = '|74373:113|:14' 
-- Equation name is 'LED_D7', type is output 
 LED_D7  = LCELL( _EQ029 $  GND);
  _EQ029 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D2 & !WR~
         #  LED_D7 &  _X009;
  _X009  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D2 & !WR~);

-- Node name is 'LED_D8' = '|74373:113|:15' 
-- Equation name is 'LED_D8', type is output 
 LED_D8  = LCELL( _EQ030 $  GND);
  _EQ030 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D3 & !WR~
         #  LED_D8 &  _X010;
  _X010  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D3 & !WR~);

-- Node name is 'LED_D9' = '|74373:113|:16' 
-- Equation name is 'LED_D9', type is output 
 LED_D9  = LCELL( _EQ031 $  GND);
  _EQ031 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D4 & !WR~
         #  LED_D9 &  _X011;
  _X011  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D4 & !WR~);

-- Node name is 'LED_D10' = '|74373:113|:17' 
-- Equation name is 'LED_D10', type is output 
 LED_D10 = LCELL( _EQ032 $  GND);
  _EQ032 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D5 & !WR~
         #  LED_D10 &  _X012;
  _X012  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D5 & !WR~);

-- Node name is 'LED_D11' = '|74373:113|:18' 
-- Equation name is 'LED_D11', type is output 
 LED_D11 = LCELL( _EQ033 $  GND);
  _EQ033 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D6 & !WR~
         #  LED_D11 &  _X013;
  _X013  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D6 & !WR~);

-- Node name is 'LED_D12' = '|74373:113|:19' 
-- Equation name is 'LED_D12', type is output 
 LED_D12 = LCELL( _EQ034 $  GND);
  _EQ034 = !A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D7 & !WR~
         #  LED_D12 &  _X014;
  _X014  = EXP(!A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D7 & !WR~);

-- Node name is 'RD_GR47LED' 
-- Equation name is 'RD_GR47LED', location is LC093, type is output.
 RD_GR47LED = LCELL( RD_GR47 $  GND);

-- Node name is 'RP_FLASH1' 
-- Equation name is 'RP_FLASH1', location is LC091, type is output.
 RP_FLASH1 = LCELL( GND $  VCC);

-- Node name is 'RP_FLASH2' 
-- Equation name is 'RP_FLASH2', location is LC089, type is output.
 RP_FLASH2 = LCELL( GND $  VCC);

-- Node name is 'TD_GR47LED' 
-- Equation name is 'TD_GR47LED', location is LC094, type is output.
 TD_GR47LED = LCELL( TD_GR47 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                  e:\riti\backup\gprs\epld\new\gprs_new.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,798K