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📄 gprs_new.rpt

📁 51单片机系统扩展超大容量存储器接口设计的cpld源码。
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Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                   Logic cells placed in LAB 'E'
        +--------- LC73 LED_D5
        | +------- LC75 LED_D6
        | | +----- LC77 LED_D7
        | | | +--- LC78 LED_D8
        | | | | +- LC80 LED_D9
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'E'
LC      | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC73 -> * - - - - | - - - - * - - - | <-- LED_D5
LC75 -> - * - - - | - - - - * - - - | <-- LED_D6
LC77 -> - - * - - | - - - - * - - - | <-- LED_D7
LC78 -> - - - * - | - - - - * - - - | <-- LED_D8
LC80 -> - - - - * | - - - - * - - - | <-- LED_D9

Pin
25   -> * * * * * | * * - * * * * * | <-- A8
12   -> * * * * * | * * - * * * * * | <-- A9
13   -> * * * * * | * * - * * * * * | <-- A10
64   -> * * * * * | * * - * * * * * | <-- A11
42   -> * * * * * | * * - * * * * * | <-- A12
41   -> * * * * * | * * - * * * * * | <-- A13
40   -> * * * * * | * * - * * * * * | <-- A14
37   -> * * * * * | * * - * * * * * | <-- A15
2    -> * * * * * | * * - * * * * * | <-- A23
70   -> * * * * * | * * - - * * * - | <-- WR~
LC38 -> * * * * * | * * * * * * * * | <-- A5
LC37 -> * * * * * | * * * * * * * * | <-- A6
LC35 -> * * * * * | * * * * * * * * | <-- A7
LC64 -> * - - - - | - * * - * - - - | <-- D0
LC62 -> - * - - - | - * * - * - - - | <-- D1
LC61 -> - - * - - | - * * - * - - - | <-- D2
LC59 -> - - - * - | - * * - * - - - | <-- D3
LC57 -> - - - - * | - * * - * - - - | <-- D4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                     Logic cells placed in LAB 'F'
        +----------- LC81 LED_D10
        | +--------- LC83 LED_D11
        | | +------- LC93 RD_GR47LED
        | | | +----- LC91 RP_FLASH1
        | | | | +--- LC89 RP_FLASH2
        | | | | | +- LC94 TD_GR47LED
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'F'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC81 -> * - - - - - | - - - - - * - - | <-- LED_D10
LC83 -> - * - - - - | - - - - - * - - | <-- LED_D11

Pin
25   -> * * - - - - | * * - * * * * * | <-- A8
12   -> * * - - - - | * * - * * * * * | <-- A9
13   -> * * - - - - | * * - * * * * * | <-- A10
64   -> * * - - - - | * * - * * * * * | <-- A11
42   -> * * - - - - | * * - * * * * * | <-- A12
41   -> * * - - - - | * * - * * * * * | <-- A13
40   -> * * - - - - | * * - * * * * * | <-- A14
37   -> * * - - - - | * * - * * * * * | <-- A15
2    -> * * - - - - | * * - * * * * * | <-- A23
99   -> - - * - - - | - - - - - * - - | <-- RD_GR47
100  -> - - - - - * | - - - - - * - - | <-- TD_GR47
70   -> * * - - - - | * * - - * * * - | <-- WR~
LC38 -> * * - - - - | * * * * * * * * | <-- A5
LC37 -> * * - - - - | * * * * * * * * | <-- A6
LC35 -> * * - - - - | * * * * * * * * | <-- A7
LC56 -> * - - - - - | - * * - - * - - | <-- D5
LC54 -> - * - - - - | - - * - - * - - | <-- D6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

           Logic cells placed in LAB 'G'
        +- LC101 LED_D12
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'G'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC101-> * | - - - - - - * - | <-- LED_D12

Pin
25   -> * | * * - * * * * * | <-- A8
12   -> * | * * - * * * * * | <-- A9
13   -> * | * * - * * * * * | <-- A10
64   -> * | * * - * * * * * | <-- A11
42   -> * | * * - * * * * * | <-- A12
41   -> * | * * - * * * * * | <-- A13
40   -> * | * * - * * * * * | <-- A14
37   -> * | * * - * * * * * | <-- A15
2    -> * | * * - * * * * * | <-- A23
70   -> * | * * - - * * * - | <-- WR~
LC38 -> * | * * * * * * * * | <-- A5
LC37 -> * | * * * * * * * * | <-- A6
LC35 -> * | * * * * * * * * | <-- A7
LC53 -> * | - - * - - - * - | <-- D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                   Logic cells placed in LAB 'H'
        +--------- LC115 CS_A~
        | +------- LC121 CS_B~
        | | +----- LC123 CS_C~
        | | | +--- LC120 CS_D~
        | | | | +- LC126 IRQ_16C554~
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'H'
LC      | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':

Pin
25   -> * * * * - | * * - * * * * * | <-- A8
12   -> * * * * - | * * - * * * * * | <-- A9
13   -> * * * * - | * * - * * * * * | <-- A10
64   -> * * * * - | * * - * * * * * | <-- A11
42   -> * * * * - | * * - * * * * * | <-- A12
41   -> * * * * - | * * - * * * * * | <-- A13
40   -> * * * * - | * * - * * * * * | <-- A14
37   -> * * * * - | * * - * * * * * | <-- A15
2    -> * * * * - | * * - * * * * * | <-- A23
75   -> - - - - * | - - - * - - - * | <-- INTA
78   -> - - - - * | - - - * - - - * | <-- INTB
LC38 -> * * * * - | * * * * * * * * | <-- A5
LC37 -> * * * * - | * * * * * * * * | <-- A6
LC35 -> * * * * - | * * * * * * * * | <-- A7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** EQUATIONS **

ALE      : INPUT;
A8       : INPUT;
A9       : INPUT;
A10      : INPUT;
A11      : INPUT;
A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
A22      : INPUT;
A23      : INPUT;
INTA     : INPUT;
INTB     : INPUT;
INTC     : INPUT;
INTD     : INPUT;
P11      : INPUT;
P14      : INPUT;
P15      : INPUT;
P31      : INPUT;
RB_FLASH1~ : INPUT;
RB_FLASH2~ : INPUT;
RD~      : INPUT;
RD_GR47  : INPUT;
TD_GR47  : INPUT;
WR~      : INPUT;

-- Node name is 'A0' = '|74373:47|:12' 
-- Equation name is 'A0', type is output 
 A0      = LCELL( _EQ001 $  GND);
  _EQ001 =  ALE &  D0
         #  A0 &  D0
         # !ALE &  A0;

-- Node name is 'A1' = '|74373:47|:13' 
-- Equation name is 'A1', type is output 
 A1      = LCELL( _EQ002 $  GND);
  _EQ002 =  ALE &  D1
         #  A1 &  D1
         # !ALE &  A1;

-- Node name is 'A2' = '|74373:47|:14' 
-- Equation name is 'A2', type is output 
 A2      = LCELL( _EQ003 $  GND);
  _EQ003 =  ALE &  D2
         #  A2 &  D2
         # !ALE &  A2;

-- Node name is 'A3' = '|74373:47|:15' 
-- Equation name is 'A3', type is output 
 A3      = LCELL( _EQ004 $  GND);
  _EQ004 =  ALE &  D3
         #  A3 &  D3
         # !ALE &  A3;

-- Node name is 'A4' = '|74373:47|:16' 
-- Equation name is 'A4', type is output 
 A4      = LCELL( _EQ005 $  GND);
  _EQ005 =  ALE &  D4
         #  A4 &  D4
         # !ALE &  A4;

-- Node name is 'A5' = '|74373:47|:17' 
-- Equation name is 'A5', type is output 
 A5      = LCELL( _EQ006 $  GND);
  _EQ006 =  ALE &  D5
         #  A5 &  D5
         # !ALE &  A5;

-- Node name is 'A6' = '|74373:47|:18' 
-- Equation name is 'A6', type is output 
 A6      = LCELL( _EQ007 $  GND);
  _EQ007 =  ALE &  D6
         #  A6 &  D6
         # !ALE &  A6;

-- Node name is 'A7' = '|74373:47|:19' 
-- Equation name is 'A7', type is output 
 A7      = LCELL( _EQ008 $  GND);
  _EQ008 =  ALE &  D7
         #  A7 &  D7
         # !ALE &  A7;

-- Node name is 'A16' = '|74373:89|:12' 
-- Equation name is 'A16', type is output 
 A16     = LCELL( _EQ009 $  GND);
  _EQ009 =  A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D0 & !WR~
         #  A16 &  _X001;
  _X001  = EXP( A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D0 & !WR~);

-- Node name is 'A17' = '|74373:89|:13' 
-- Equation name is 'A17', type is output 
 A17     = LCELL( _EQ010 $  GND);
  _EQ010 =  A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D1 & !WR~
         #  A17 &  _X002;
  _X002  = EXP( A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D1 & !WR~);

-- Node name is 'A18' = '|74373:89|:14' 
-- Equation name is 'A18', type is output 
 A18     = LCELL( _EQ011 $  GND);
  _EQ011 =  A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D2 & !WR~
         #  A18 &  _X003;
  _X003  = EXP( A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D2 & !WR~);

-- Node name is 'A19' = '|74373:89|:15' 
-- Equation name is 'A19', type is output 
 A19     = LCELL( _EQ012 $  GND);
  _EQ012 =  A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D3 & !WR~
         #  A19 &  _X004;
  _X004  = EXP( A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D3 & !WR~);

-- Node name is 'A20' = '|74373:89|:16' 
-- Equation name is 'A20', type is output 
 A20     = LCELL( _EQ013 $  GND);
  _EQ013 =  A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 &  D4 & !WR~
         #  A20 &  _X005;
  _X005  = EXP( A5 & !A6 & !A7 &  A8 &  A9 &  A10 &  A11 &  A12 &  A13 &  A14 & 
              A15 &  A23 & !D4 & !WR~);

-- Node name is 'A21' = '|74373:89|:17' 

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