📄 gprs_new.rpt
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37 (49) (D) INPUT 0 0 0 0 0 22 1 A15
1 (3) (A) INPUT 0 0 0 0 0 2 0 A22
2 (1) (A) INPUT 0 0 0 0 0 24 1 A23
27 64 D BIDIR 0 0 0 1 0 3 0 D0
28 62 D BIDIR 0 0 0 1 0 3 0 D1
29 61 D OPNDRN 0 0 0 10 3 3 0 D2
30 59 D OPNDRN 0 0 0 10 3 3 0 D3
31 57 D BIDIR 0 0 0 1 0 3 0 D4
32 56 D BIDIR 0 0 0 1 0 3 0 D5
33 54 D BIDIR 0 0 0 1 0 2 0 D6
35 53 D BIDIR 0 0 0 1 0 2 0 D7
75 (113) (H) INPUT 0 0 0 0 0 2 0 INTA
78 (118) (H) INPUT 0 0 0 0 0 2 0 INTB
83 (125) (H) INPUT 0 0 0 0 0 1 0 INTC
77 (117) (H) INPUT 0 0 0 0 0 1 0 INTD
68 (104) (G) INPUT 0 0 0 0 0 0 0 P11
55 (86) (F) INPUT 0 0 0 0 0 0 0 P14
54 (85) (F) INPUT 0 0 0 0 0 0 0 P15
56 (88) (F) INPUT 0 0 0 0 0 0 0 P31
44 (70) (E) INPUT 0 0 0 0 0 1 0 RB_FLASH1~
45 (72) (E) INPUT 0 0 0 0 0 1 0 RB_FLASH2~
71 (109) (G) INPUT 0 0 0 0 0 2 1 RD~
99 (6) (A) INPUT 0 0 0 0 0 1 0 RD_GR47
100 (5) (A) INPUT 0 0 0 0 0 1 0 TD_GR47
70 (107) (G) INPUT 0 0 0 0 0 15 0 WR~
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
16 46 C OUTPUT t 0 0 0 1 2 1 0 A0
17 45 C OUTPUT t 0 0 0 1 2 1 0 A1
19 43 C OUTPUT t 0 0 0 1 2 1 0 A2
20 41 C OUTPUT t 0 0 0 1 2 1 0 A3
21 40 C OUTPUT t 0 0 0 1 2 1 0 A4
22 38 C OUTPUT t 0 0 0 1 2 22 1 A5
23 37 C OUTPUT t 0 0 0 1 2 22 1 A6
24 35 C OUTPUT t 0 0 0 1 2 22 1 A7
10 22 B OUTPUT t 1 0 0 10 5 1 0 A16
9 24 B OUTPUT t 1 0 0 10 5 1 0 A17
8 25 B OUTPUT t 1 0 0 10 5 1 0 A18
7 27 B OUTPUT t 1 0 0 10 5 1 0 A19
6 29 B OUTPUT t 1 0 0 10 5 1 0 A20
5 30 B OUTPUT t 1 0 0 10 5 1 0 A21
76 115 H OUTPUT t 0 0 0 9 3 0 0 CS_A~
80 121 H OUTPUT t 0 0 0 9 3 0 0 CS_B~
81 123 H OUTPUT t 0 0 0 9 3 0 0 CS_C~
79 120 H OUTPUT t 0 0 0 9 3 0 0 CS_D~
94 13 A OUTPUT t 0 0 0 2 0 0 0 CS_FLASH1~
93 14 A OUTPUT t 0 0 0 2 0 0 0 CS_FLASH2~
98 8 A OUTPUT t 0 0 0 10 3 0 0 CS_LED
92 16 A OUTPUT t 0 0 0 9 0 0 0 CS_SRAM~
27 64 D TRI t 0 0 0 1 0 3 0 D0
28 62 D TRI t 0 0 0 1 0 3 0 D1
29 61 D OPNDRN t 0 0 0 10 3 3 0 D2
30 59 D OPNDRN t 0 0 0 10 3 3 0 D3
31 57 D TRI t 0 0 0 1 0 3 0 D4
32 56 D TRI t 0 0 0 1 0 3 0 D5
33 54 D TRI t 0 0 0 1 0 2 0 D6
35 53 D TRI t 0 0 0 1 0 2 0 D7
96 11 A OUTPUT t 0 0 0 0 0 0 0 INTSEL
84 126 H OUTPUT t 0 0 0 2 0 0 0 IRQ_16C554~
46 73 E OUTPUT t 1 0 0 10 5 1 0 LED_D5
47 75 E OUTPUT t 1 0 0 10 5 1 0 LED_D6
48 77 E OUTPUT t 1 0 0 10 5 1 0 LED_D7
49 78 E OUTPUT t 1 0 0 10 5 1 0 LED_D8
50 80 E OUTPUT t 1 0 0 10 5 1 0 LED_D9
52 81 F OUTPUT t 1 0 0 10 5 1 0 LED_D10
53 83 F OUTPUT t 1 0 0 10 5 1 0 LED_D11
65 101 G OUTPUT t 1 0 0 10 5 1 0 LED_D12
60 93 F OUTPUT t 0 0 0 1 0 0 0 RD_GR47LED
58 91 F OUTPUT t 0 0 0 0 0 0 0 RP_FLASH1
57 89 F OUTPUT t 0 0 0 0 0 0 0 RP_FLASH2
61 94 F OUTPUT t 0 0 0 1 0 0 0 TD_GR47LED
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(36) 51 D SOFT s t 0 0 0 10 3 0 0 D7~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC13 CS_FLASH1~
| +------- LC14 CS_FLASH2~
| | +----- LC8 CS_LED
| | | +--- LC16 CS_SRAM~
| | | | +- LC11 INTSEL
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
25 -> - - * * - | * * - * * * * * | <-- A8
12 -> - - * * - | * * - * * * * * | <-- A9
13 -> - - * * - | * * - * * * * * | <-- A10
64 -> - - * * - | * * - * * * * * | <-- A11
42 -> - - * * - | * * - * * * * * | <-- A12
41 -> - - * * - | * * - * * * * * | <-- A13
40 -> - - * * - | * * - * * * * * | <-- A14
37 -> - - * * - | * * - * * * * * | <-- A15
1 -> * * - - - | * - - - - - - - | <-- A22
2 -> * * * * - | * * - * * * * * | <-- A23
70 -> - - * - - | * * - - * * * - | <-- WR~
LC38 -> - - * - - | * * * * * * * * | <-- A5
LC37 -> - - * - - | * * * * * * * * | <-- A6
LC35 -> - - * - - | * * * * * * * * | <-- A7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------- LC22 A16
| +--------- LC24 A17
| | +------- LC25 A18
| | | +----- LC27 A19
| | | | +--- LC29 A20
| | | | | +- LC30 A21
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'B'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC22 -> * - - - - - | - * - - - - - - | <-- A16
LC24 -> - * - - - - | - * - - - - - - | <-- A17
LC25 -> - - * - - - | - * - - - - - - | <-- A18
LC27 -> - - - * - - | - * - - - - - - | <-- A19
LC29 -> - - - - * - | - * - - - - - - | <-- A20
LC30 -> - - - - - * | - * - - - - - - | <-- A21
Pin
25 -> * * * * * * | * * - * * * * * | <-- A8
12 -> * * * * * * | * * - * * * * * | <-- A9
13 -> * * * * * * | * * - * * * * * | <-- A10
64 -> * * * * * * | * * - * * * * * | <-- A11
42 -> * * * * * * | * * - * * * * * | <-- A12
41 -> * * * * * * | * * - * * * * * | <-- A13
40 -> * * * * * * | * * - * * * * * | <-- A14
37 -> * * * * * * | * * - * * * * * | <-- A15
2 -> * * * * * * | * * - * * * * * | <-- A23
70 -> * * * * * * | * * - - * * * - | <-- WR~
LC38 -> * * * * * * | * * * * * * * * | <-- A5
LC37 -> * * * * * * | * * * * * * * * | <-- A6
LC35 -> * * * * * * | * * * * * * * * | <-- A7
LC64 -> * - - - - - | - * * - * - - - | <-- D0
LC62 -> - * - - - - | - * * - * - - - | <-- D1
LC61 -> - - * - - - | - * * - * - - - | <-- D2
LC59 -> - - - * - - | - * * - * - - - | <-- D3
LC57 -> - - - - * - | - * * - * - - - | <-- D4
LC56 -> - - - - - * | - * * - - * - - | <-- D5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------- LC46 A0
| +------------- LC45 A1
| | +----------- LC43 A2
| | | +--------- LC41 A3
| | | | +------- LC40 A4
| | | | | +----- LC38 A5
| | | | | | +--- LC37 A6
| | | | | | | +- LC35 A7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'C'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC46 -> * - - - - - - - | - - * - - - - - | <-- A0
LC45 -> - * - - - - - - | - - * - - - - - | <-- A1
LC43 -> - - * - - - - - | - - * - - - - - | <-- A2
LC41 -> - - - * - - - - | - - * - - - - - | <-- A3
LC40 -> - - - - * - - - | - - * - - - - - | <-- A4
LC38 -> - - - - - * - - | * * * * * * * * | <-- A5
LC37 -> - - - - - - * - | * * * * * * * * | <-- A6
LC35 -> - - - - - - - * | * * * * * * * * | <-- A7
Pin
69 -> * * * * * * * * | - - * - - - - - | <-- ALE
LC64 -> * - - - - - - - | - * * - * - - - | <-- D0
LC62 -> - * - - - - - - | - * * - * - - - | <-- D1
LC61 -> - - * - - - - - | - * * - * - - - | <-- D2
LC59 -> - - - * - - - - | - * * - * - - - | <-- D3
LC57 -> - - - - * - - - | - * * - * - - - | <-- D4
LC56 -> - - - - - * - - | - * * - - * - - | <-- D5
LC54 -> - - - - - - * - | - - * - - * - - | <-- D6
LC53 -> - - - - - - - * | - - * - - - * - | <-- D7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------- LC64 D0
| +--------------- LC62 D1
| | +------------- LC61 D2
| | | +----------- LC59 D3
| | | | +--------- LC57 D4
| | | | | +------- LC56 D5
| | | | | | +----- LC54 D6
| | | | | | | +--- LC51 D7~1
| | | | | | | | +- LC53 D7
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
25 -> - - * * - - - * - | * * - * * * * * | <-- A8
12 -> - - * * - - - * - | * * - * * * * * | <-- A9
13 -> - - * * - - - * - | * * - * * * * * | <-- A10
64 -> - - * * - - - * - | * * - * * * * * | <-- A11
42 -> - - * * - - - * - | * * - * * * * * | <-- A12
41 -> - - * * - - - * - | * * - * * * * * | <-- A13
40 -> - - * * - - - * - | * * - * * * * * | <-- A14
37 -> - - * * - - - * - | * * - * * * * * | <-- A15
2 -> - - * * - - - * - | * * - * * * * * | <-- A23
75 -> - - - - * - - - - | - - - * - - - * | <-- INTA
78 -> - - - - - * - - - | - - - * - - - * | <-- INTB
83 -> - - - - - - * - - | - - - * - - - - | <-- INTC
77 -> - - - - - - - - * | - - - * - - - - | <-- INTD
44 -> * - - - - - - - - | - - - * - - - - | <-- RB_FLASH1~
45 -> - * - - - - - - - | - - - * - - - - | <-- RB_FLASH2~
71 -> - - * * - - - * - | - - - * - - - - | <-- RD~
LC38 -> - - * * - - - * - | * * * * * * * * | <-- A5
LC37 -> - - * * - - - * - | * * * * * * * * | <-- A6
LC35 -> - - * * - - - * - | * * * * * * * * | <-- A7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
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