gprs_new.rpt

51单片机系统扩展超大容量存储器接口设计的cpld源码。

Project Information                  e:\riti\backup\gprs\epld\new\gprs_new.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/26/2005 21:58:12

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

EPM7128   EPM7128STC100-15 25       36       8      45      14          35 %

User Pins:                 25       36       8  



Project Information                  e:\riti\backup\gprs\epld\new\gprs_new.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Primitive 'INTSEL' is stuck at VCC
Warning: Primitive 'RP_FLASH1' is stuck at VCC
Warning: Primitive 'RP_FLASH2' is stuck at VCC
Info: Reserved unused input pin 'P31' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'P15' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'P11' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'P14' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board


Project Information                  e:\riti\backup\gprs\epld\new\gprs_new.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

EPM7128@69                        ALE
EPM7128@16                        A0
EPM7128@17                        A1
EPM7128@19                        A2
EPM7128@20                        A3
EPM7128@21                        A4
EPM7128@22                        A5
EPM7128@23                        A6
EPM7128@24                        A7
EPM7128@25                        A8
EPM7128@12                        A9
EPM7128@13                        A10
EPM7128@64                        A11
EPM7128@42                        A12
EPM7128@41                        A13
EPM7128@40                        A14
EPM7128@37                        A15
EPM7128@10                        A16
EPM7128@9                         A17
EPM7128@8                         A18
EPM7128@7                         A19
EPM7128@6                         A20
EPM7128@5                         A21
EPM7128@1                         A22
EPM7128@2                         A23
EPM7128@76                        CS_A~
EPM7128@80                        CS_B~
EPM7128@81                        CS_C~
EPM7128@79                        CS_D~
EPM7128@94                        CS_FLASH1~
EPM7128@93                        CS_FLASH2~
EPM7128@98                        CS_LED
EPM7128@92                        CS_SRAM~
EPM7128@27                        D0
EPM7128@28                        D1
EPM7128@29                        D2
EPM7128@30                        D3
EPM7128@31                        D4
EPM7128@32                        D5
EPM7128@33                        D6
EPM7128@35                        D7
EPM7128@75                        INTA
EPM7128@78                        INTB
EPM7128@83                        INTC
EPM7128@77                        INTD
EPM7128@96                        INTSEL
EPM7128@84                        IRQ_16C554~
EPM7128@46                        LED_D5
EPM7128@47                        LED_D6
EPM7128@48                        LED_D7
EPM7128@49                        LED_D8
EPM7128@50                        LED_D9
EPM7128@52                        LED_D10
EPM7128@53                        LED_D11
EPM7128@65                        LED_D12
EPM7128@68                        P11
EPM7128@55                        P14
EPM7128@54                        P15
EPM7128@56                        P31
EPM7128@44                        RB_FLASH1~
EPM7128@45                        RB_FLASH2~
EPM7128@71                        RD~
EPM7128@99                        RD_GR47
EPM7128@60                        RD_GR47LED
EPM7128@58                        RP_FLASH1
EPM7128@57                        RP_FLASH2
EPM7128@100                       TD_GR47
EPM7128@61                        TD_GR47LED
EPM7128@70                        WR~


Project Information                  e:\riti\backup\gprs\epld\new\gprs_new.rpt

** FILE HIERARCHY **



|74373:47|
|74373:113|
|74373:89|
|74138:58|
|74244:241|
|74139:256|


Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

***** Logic for device 'EPM7128' compiled without errors.




Device: EPM7128STC100-15

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF



Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** ERROR SUMMARY **

Info: Chip 'EPM7128' in device 'EPM7128STC100-15' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                 I                  
                             C C                 R                  
                             S S                 Q                  
                       R     _ _ C             R _                  
                 T R   E     F F S             E 1                  
                 D D C S I   L L _ V           S 6                  
                 _ _ S E N   A A S C           E C   V C C C     C  
                 G G _ R T   S S R C           R 5 I C S S S I I S  
                 R R L V S G H H A I G G G G G V 5 N C _ _ _ N N _  
                 4 4 E E E N 1 2 M N N N N N N E 4 T I C B D T T A  
                 7 7 D D L D ~ ~ ~ T D D D D D D ~ C O ~ ~ ~ B D ~  
               ----------------------------------------------------_ 
              / 100  98  96  94  92  90  88  86  84  82  80  78  76   |_ 
             /     99  97  95  93  91  89  87  85  83  81  79  77    | 
        A22 |  1                                                    75 | INTA 
        A23 |  2                                                    74 | GND 
      VCCIO |  3                                                    73 | #TDO 
       #TDI |  4                                                    72 | RESERVED 
        A21 |  5                                                    71 | RD~ 
        A20 |  6                                                    70 | WR~ 
        A19 |  7                                                    69 | ALE 
        A18 |  8                                                    68 | P11 
        A17 |  9                                                    67 | RESERVED 
        A16 | 10                                                    66 | VCCIO 
        GND | 11                                                    65 | LED_D12 
         A9 | 12                                                    64 | A11 
        A10 | 13                 EPM7128STC100-15                   63 | RESERVED 
   RESERVED | 14                                                    62 | #TCK 
       #TMS | 15                                                    61 | TD_GR47LED 
         A0 | 16                                                    60 | RD_GR47LED 
         A1 | 17                                                    59 | GND 
      VCCIO | 18                                                    58 | RP_FLASH1 
         A2 | 19                                                    57 | RP_FLASH2 
         A3 | 20                                                    56 | P31 
         A4 | 21                                                    55 | P14 
         A5 | 22                                                    54 | P15 
         A6 | 23                                                    53 | LED_D11 
         A7 | 24                                                    52 | LED_D10 
         A8 | 25                                                    51 | VCCIO 
            |      27  29  31  33  35  37  39  41  43  45  47  49  _| 
             \   26  28  30  32  34  36  38  40  42  44  46  48  50   | 
              \----------------------------------------------------- 
                 G D D D D D D D V D R A G V A A A G R R L L L L L  
                 N 0 1 2 3 4 5 6 C 7 E 1 N C 1 1 1 N B B E E E E E  
                 D               C   S 5 D C 4 3 2 D _ _ D D D D D  
                                 I   E     I         F F _ _ _ _ _  
                                 O   R     N         L L D D D D D  
                                     V     T         A A 5 6 7 8 9  
                                     E               S S            
                                     D               H H            
                                                     1 2            
                                                     ~ ~            
                                                                    


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     5/16( 31%)   9/10( 90%)   0/16(  0%)  14/36( 38%) 
B:    LC17 - LC32     6/16( 37%)   9/10( 90%)   6/16( 37%)  25/36( 69%) 
C:    LC33 - LC48     8/16( 50%)  10/10(100%)   0/16(  0%)  17/36( 47%) 
D:    LC49 - LC64     9/16( 56%)   9/10( 90%)   0/16(  0%)  19/36( 52%) 
E:    LC65 - LC80     5/16( 31%)  10/10(100%)   5/16( 31%)  23/36( 63%) 
F:    LC81 - LC96     6/16( 37%)  10/10(100%)   2/16( 12%)  19/36( 52%) 
G:   LC97 - LC112     1/16(  6%)   7/10( 70%)   1/16(  6%)  15/36( 41%) 
H:  LC113 - LC128     5/16( 31%)   9/10( 90%)   0/16(  0%)  14/36( 38%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            73/80     ( 91%)
Total logic cells used:                         45/128    ( 35%)
Total shareable expanders used:                 14/128    ( 10%)
Total Turbo logic cells used:                   45/128    ( 35%)
Total shareable expanders not available (n/a):   0/128    (  0%)
Average fan-in:                                  8.06
Total fan-in:                                   363

Total input pins required:                      25
Total fast input logic cells required:           0
Total output pins required:                     36
Total bidirectional pins required:               8
Total reserved pins required                     4
Total logic cells required:                     45
Total flipflops required:                        0
Total product terms required:                   90
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          14

Synthesized logic cells:                         1/ 128   (  0%)



Device-Specific Information:         e:\riti\backup\gprs\epld\new\gprs_new.rpt
EPM7128

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  69  (105)  (G)      INPUT               0      0   0    0    0    8    0  ALE
  25   (33)  (C)      INPUT               0      0   0    0    0   22    1  A8
  12   (21)  (B)      INPUT               0      0   0    0    0   22    1  A9
  13   (19)  (B)      INPUT               0      0   0    0    0   22    1  A10
  64   (99)  (G)      INPUT               0      0   0    0    0   22    1  A11
  42   (69)  (E)      INPUT               0      0   0    0    0   22    1  A12
  41   (67)  (E)      INPUT               0      0   0    0    0   22    1  A13
  40   (65)  (E)      INPUT               0      0   0    0    0   22    1  A14