📄 ioat91sam7s64.h
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// - ----------------------------------------------------------------------------
// - ATMEL Microcontroller Software Support - ROUSSET -
// - ----------------------------------------------------------------------------
// - The software is delivered "AS IS" without warranty or condition of any
// - kind, either express, implied or statutory. This includes without
// - limitation any warranty or condition with respect to merchantability or
// - fitness for any particular purpose, or against the infringements of
// - intellectual property rights of others.
// - ----------------------------------------------------------------------------
// - File Name : AT91SAM7S64.h
// - Object : AT91SAM7S64 definitions
// - Generated : AT91 SW Application Group 09/01/2004 (10:02:06)
// -
// - CVS Reference : /AT91SAM7S64.pl/1.15/Mon Aug 30 08:48:08 2004//
// - CVS Reference : /SYS_SAM7Sxxx.pl/1.5/Mon Aug 30 13:17:50 2004//
// - CVS Reference : /MC_SAM02.pl/1.3/Mon Mar 08 09:22:24 2004//
// - CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
// - CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// - CVS Reference : /PMC_SAM.pl/1.10/Mon May 10 12:08:48 2004//
// - CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// - CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
// - CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:26 2002//
// - CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
// - CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:40 2002//
// - CVS Reference : /TC_1753B.pl/1.4/Mon Mar 01 14:10:12 2004//
// - CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:08 2003//
// - CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
// - CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
// - CVS Reference : /PWM_SAM.pl/1.5/Wed Apr 14 12:02:52 2004//
// - ----------------------------------------------------------------------------
#ifndef AT91SAM7S64_H
#define AT91SAM7S64_H
#ifdef __IAR_SYSTEMS_ICC__
typedef volatile unsigned int AT91_REG;// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
typedef struct _AT91S_SYSC {
AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register
AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register
AT91_REG SYSC_AIC_IVR; // IRQ Vector Register
AT91_REG SYSC_AIC_FVR; // FIQ Vector Register
AT91_REG SYSC_AIC_ISR; // Interrupt Status Register
AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register
AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register
AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register
AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register
AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register
AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register
AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register
AT91_REG SYSC_AIC_SPU; // Spurious Vector Register
AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register
AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register
AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved2[45]; //
AT91_REG SYSC_DBGU_CR; // Control Register
AT91_REG SYSC_DBGU_MR; // Mode Register
AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register
AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register
AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register
AT91_REG SYSC_DBGU_CSR; // Channel Status Register
AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register
AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register
AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved3[7]; //
AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register
AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register
AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved4[45]; //
AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register
AT91_REG SYSC_DBGU_RCR; // Receive Counter Register
AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register
AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register
AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register
AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register
AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register
AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register
AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved5[54]; //
AT91_REG SYSC_PIOA_PER; // PIO Enable Register
AT91_REG SYSC_PIOA_PDR; // PIO Disable Register
AT91_REG SYSC_PIOA_PSR; // PIO Status Register
AT91_REG Reserved6[1]; //
AT91_REG SYSC_PIOA_OER; // Output Enable Register
AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr
AT91_REG SYSC_PIOA_OSR; // Output Status Register
AT91_REG Reserved7[1]; //
AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register
AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register
AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved8[1]; //
AT91_REG SYSC_PIOA_SODR; // Set Output Data Register
AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register
AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register
AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register
AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register
AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register
AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register
AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register
AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register
AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register
AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved9[1]; //
AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register
AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register
AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register
AT91_REG Reserved10[1]; //
AT91_REG SYSC_PIOA_ASR; // Select A Register
AT91_REG SYSC_PIOA_BSR; // Select B Register
AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved11[9]; //
AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register
AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register
AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved12[469]; //
AT91_REG SYSC_PMC_SCER; // System Clock Enable Register
AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register
AT91_REG SYSC_PMC_SCSR; // System Clock Status Register
AT91_REG Reserved13[1]; //
AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register
AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved14[1]; //
AT91_REG SYSC_PMC_MOR; // Main Oscillator Register
AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved15[1]; //
AT91_REG SYSC_PMC_PLLR; // PLL Register
AT91_REG SYSC_PMC_MCKR; // Master Clock Register
AT91_REG Reserved16[3]; //
AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register
AT91_REG SYSC_PMC_IER; // Interrupt Enable Register
AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register
AT91_REG SYSC_PMC_SR; // Status Register
AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved17[36]; //
AT91_REG SYSC_RSTC_RCR; // Reset Control Register
AT91_REG SYSC_RSTC_RSR; // Reset Status Register
AT91_REG SYSC_RSTC_RMR; // Reset Mode Register
AT91_REG Reserved18[5]; //
AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register
AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register
AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register
AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register
AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register
AT91_REG SYSC_PITC_PISR; // Period Interval Status Register
AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register
AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register
AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register
AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register
AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved19[5]; //
AT91_REG SYSC_SYSC_VREG; // Voltage Regulator Mode Register
} AT91S_SYSC, *AT91PS_SYSC;
// -------- VREG : (SYSC Offset: 0xd60) Voltage Regulator Mode Register --------
#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
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