📄 at91sam7s64.inc
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^ 0 ;- AT91S_DBGU
DBGU_CR # 4 ;- Control Register
DBGU_MR # 4 ;- Mode Register
DBGU_IER # 4 ;- Interrupt Enable Register
DBGU_IDR # 4 ;- Interrupt Disable Register
DBGU_IMR # 4 ;- Interrupt Mask Register
DBGU_CSR # 4 ;- Channel Status Register
DBGU_RHR # 4 ;- Receiver Holding Register
DBGU_THR # 4 ;- Transmitter Holding Register
DBGU_BRGR # 4 ;- Baud Rate Generator Register
# 28 ;- Reserved
DBGU_C1R # 4 ;- Chip ID1 Register
DBGU_C2R # 4 ;- Chip ID2 Register
DBGU_FNTR # 4 ;- Force NTRST Register
# 180 ;- Reserved
DBGU_RPR # 4 ;- Receive Pointer Register
DBGU_RCR # 4 ;- Receive Counter Register
DBGU_TPR # 4 ;- Transmit Pointer Register
DBGU_TCR # 4 ;- Transmit Counter Register
DBGU_RNPR # 4 ;- Receive Next Pointer Register
DBGU_RNCR # 4 ;- Receive Next Counter Register
DBGU_TNPR # 4 ;- Transmit Next Pointer Register
DBGU_TNCR # 4 ;- Transmit Next Counter Register
DBGU_PTCR # 4 ;- PDC Transfer Control Register
DBGU_PTSR # 4 ;- PDC Transfer Status Register
;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type
AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity
AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity
AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Peripheral Data Controller
;- *****************************************************************************
^ 0 ;- AT91S_PDC
PDC_RPR # 4 ;- Receive Pointer Register
PDC_RCR # 4 ;- Receive Counter Register
PDC_TPR # 4 ;- Transmit Pointer Register
PDC_TCR # 4 ;- Transmit Counter Register
PDC_RNPR # 4 ;- Receive Next Pointer Register
PDC_RNCR # 4 ;- Receive Next Counter Register
PDC_TNPR # 4 ;- Transmit Next Pointer Register
PDC_TNCR # 4 ;- Transmit Next Counter Register
PDC_PTCR # 4 ;- PDC Transfer Control Register
PDC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
;- *****************************************************************************
^ 0 ;- AT91S_PIO
PIO_PER # 4 ;- PIO Enable Register
PIO_PDR # 4 ;- PIO Disable Register
PIO_PSR # 4 ;- PIO Status Register
# 4 ;- Reserved
PIO_OER # 4 ;- Output Enable Register
PIO_ODR # 4 ;- Output Disable Registerr
PIO_OSR # 4 ;- Output Status Register
# 4 ;- Reserved
PIO_IFER # 4 ;- Input Filter Enable Register
PIO_IFDR # 4 ;- Input Filter Disable Register
PIO_IFSR # 4 ;- Input Filter Status Register
# 4 ;- Reserved
PIO_SODR # 4 ;- Set Output Data Register
PIO_CODR # 4 ;- Clear Output Data Register
PIO_ODSR # 4 ;- Output Data Status Register
PIO_PDSR # 4 ;- Pin Data Status Register
PIO_IER # 4 ;- Interrupt Enable Register
PIO_IDR # 4 ;- Interrupt Disable Register
PIO_IMR # 4 ;- Interrupt Mask Register
PIO_ISR # 4 ;- Interrupt Status Register
PIO_MDER # 4 ;- Multi-driver Enable Register
PIO_MDDR # 4 ;- Multi-driver Disable Register
PIO_MDSR # 4 ;- Multi-driver Status Register
# 4 ;- Reserved
PIO_PPUDR # 4 ;- Pull-up Disable Register
PIO_PPUER # 4 ;- Pull-up Enable Register
PIO_PPUSR # 4 ;- Pad Pull-up Status Register
# 4 ;- Reserved
PIO_ASR # 4 ;- Select A Register
PIO_BSR # 4 ;- Select B Register
PIO_ABSR # 4 ;- AB Select Status Register
# 36 ;- Reserved
PIO_OWER # 4 ;- Output Write Enable Register
PIO_OWDR # 4 ;- Output Write Disable Register
PIO_OWSR # 4 ;- Output Write Status Register
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Clock Generator Controler
;- *****************************************************************************
^ 0 ;- AT91S_CKGR
CKGR_MOR # 4 ;- Main Oscillator Register
CKGR_MCFR # 4 ;- Main Clock Frequency Register
# 4 ;- Reserved
CKGR_PLLR # 4 ;- PLL Register
;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable
AT91C_CKGR_OSCBYPASS EQU (0x1:SHL:1) ;- (CKGR) Main Oscillator Bypass
AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time
;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency
AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready
;- -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
AT91C_CKGR_DIV EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected
AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
AT91C_CKGR_PLLCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL Counter
AT91C_CKGR_OUT EQU (0x3:SHL:14) ;- (CKGR) PLL Output Frequency Range
AT91C_CKGR_OUT_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_OUT_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_OUT_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_OUT_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_MUL EQU (0x7FF:SHL:16) ;- (CKGR) PLL Multiplier
AT91C_CKGR_USBDIV EQU (0x3:SHL:28) ;- (CKGR) Divider for USB Clocks
AT91C_CKGR_USBDIV_0 EQU (0x0:SHL:28) ;- (CKGR) Divider output is PLL clock output
AT91C_CKGR_USBDIV_1 EQU (0x1:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 2
AT91C_CKGR_USBDIV_2 EQU (0x2:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 4
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Power Management Controler
;- *****************************************************************************
^ 0 ;- AT91S_PMC
PMC_SCER # 4 ;- System Clock Enable Register
PMC_SCDR # 4 ;- System Clock Disable Register
PMC_SCSR # 4 ;- System Clock Status Register
# 4 ;- Reserved
PMC_PCER # 4 ;- Peripheral Clock Enable Register
PMC_PCDR # 4 ;- Peripheral Clock Disable Register
PMC_PCSR # 4 ;- Peripheral Clock Status Register
# 4 ;- Reserved
PMC_MOR # 4 ;- Main Oscillator Register
PMC_MCFR # 4 ;- Main Clock Frequency Register
# 4 ;- Reserved
PMC_PLLR # 4 ;- PLL Register
PMC_MCKR # 4 ;- Master Clock Register
# 12 ;- Reserved
PMC_PCKR # 32 ;- Programmable Clock Register
PMC_IER # 4 ;- Interrupt Enable Register
PMC_IDR # 4 ;- Interrupt Disable Register
PMC_SR # 4 ;- Status Register
PMC_IMR # 4 ;- Interrupt Mask Register
;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock
AT91C_PMC_UDP EQU (0x1:SHL:7) ;- (PMC) USB Device Port Clock
AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output
;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
;- -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
;- -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
;- -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection
AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler
AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock
AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2
AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4
AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8
AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16
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