basic_ice.dat

EMB91SAM7S64开发板(全套资料)

Com *     ATMEL Microcontroller Software Support  -  ROUSSET  -
Com *--------------------------------------------------------------------------------------
Com *The software is delivered "AS IS" without warranty or condition of any
Com *kind, either express, implied or statutory. This includes without
Com *limitation any warranty or condition with respect to merchantability or
Com *fitness for any particular purpose, or against the infringements of
Com *intellectual property rights of others.
Com *--------------------------------------------------------------------------------------
Com *File Name               : File Basic_ICE.dat
Com *Object                  : Script file for axd debugger
Com *
Com *1.0 08/Dec/04   JPP     : Creation
Com *--------------------------------------------------------------------------------------
Com <---- This command is the comment command.
Com Enable the semihosting. If you don't use printf and/or scanf functions, set semihosting_enabled to 0.
spp semihosting_enabled 1

Com Define the top of memory to store the buffer for semihosting calls.
Com Needed when working with an ICE Interface and if you use C printf/scanf functions in your code.
echo on
let $top_of_memory 0x00203600
echo off
Com Disable all vector catch to not have AXD to warn you that a vector exception has been caught.
spp vector_catch 0x0

Com Watchdog Disable
Com     AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
setmem 0xFFFFFD44 0x00008000 32

Com  Set Flash Waite sate
Com Single Cycle Access at Up to 30 MHz
Com if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN)
Com A page erase is performed before programming.
Com AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;

setmem 0xFFFFFF60 0x00320100 32 

Com Set PLL
Com  -1- Enabling the Main Oscillator:
Com *#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20)   (PMC) Main Oscillator Register
Com *#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C)   (PMC) PLL Register
Com *#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30)   (PMC) Master Clock Register

Com *pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) |     0x0000 0600
Com                           AT91C_CKGR_MOSCEN ));           0x0000 0001 
echo on
setmem 0xFFFFFC20 0x00000601 32
echo off
Com  -2- Wait
Com  -3- Setting PLL and divider:
Com  - div by 5 Fin = 3,6864 =(18,432 / 5)
Com  - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
Com  for 96 MHz the erroe is 0.16%
Com  Field out NOT USED = 0
Com  PLLCOUNT pll startup time esrtimate at : 0.844 ms
Com  PLLCOUNT 28 = 0.000844 /(1/32768)
Com        pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |        0x0000 0005
Com                          (AT91C_CKGR_PLLCOUNT & (28<<8))  0x0000 1C00
Com                          (AT91C_CKGR_MUL & (25<<16)));    0x0019 0000 
echo on
setmem 0xFFFFFC2C 0x00191C05 32
echo off
Com  -2- Wait
Com  -5- Selection of Master Clock and Processor Clock
Com  select the PLL clock divided by 2
Com 	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |      0x0000 0003
Com                            AT91C_PMC_PRES_CLK_2 ;     0x0000 0004
echo on
setmem 0xFFFFFC30 0x00000007 32
Com  "------------------------------- PLL  Enable "

mem 0x00100000 +0 32 hex 
mem 0x00200000 +0 32 hex 

setmem 0x0 0x00000000 32
mem 0x0 +0 32 hex
Com SET remap if 0x0 if than 0x0
setmem 0xFFFFFF00 0x01 32

echo off
echo on

Com Load file
ld BasicTWI.axf