at91sam7s64.rdf

EMB91SAM7S64开发板(全套资料)

# ----------------------------------------------------------------------------
#          ATMEL Microcontroller Software Support  -  ROUSSET  -
# ----------------------------------------------------------------------------
#  The software is delivered "AS IS" without warranty or condition of any
#  kind, either express, implied or statutory. This includes without
#  limitation any warranty or condition with respect to merchantability or
#  fitness for any particular purpose, or against the infringements of
#  intellectual property rights of others.
# ----------------------------------------------------------------------------
# File Name           : AT91SAM7S64.h
# Object              : AT91SAM7S64 definitions
# Generated           : AT91 SW Application Group  09/01/2004 (10:02:06)
# 
# CVS Reference       : /AT91SAM7S64.pl/1.15/Mon Aug 30 08:48:08 2004//
# CVS Reference       : /SYS_SAM7Sxxx.pl/1.5/Mon Aug 30 13:17:50 2004//
# CVS Reference       : /MC_SAM02.pl/1.3/Mon Mar 08 09:22:24 2004//
# CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
# CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
# CVS Reference       : /PMC_SAM.pl/1.10/Mon May 10 12:08:48 2004//
# CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
# CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
# CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:26 2002//
# CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
# CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:40 2002//
# CVS Reference       : /TC_1753B.pl/1.4/Mon Mar 01 14:10:12 2004//
# CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:08 2003//
# CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
# CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
# CVS Reference       : /PWM_SAM.pl/1.5/Wed Apr 14 12:02:52 2004//
# ----------------------------------------------------------------------------

rdf.version=1

~sysinclude=arm_default.rdf
~sysinclude=arm_status.rdf
# ========== Register definition for SYSC peripheral ========== 
AT91C_SYSC_SYSC_VREG.name="AT91C_SYSC_SYSC_VREG"
AT91C_SYSC_SYSC_VREG.description="Voltage Regulator Mode Register"
AT91C_SYSC_SYSC_VREG.helpkey="Voltage Regulator Mode Register"
AT91C_SYSC_SYSC_VREG.access=memorymapped
AT91C_SYSC_SYSC_VREG.address=0xFFFFFD60
AT91C_SYSC_SYSC_VREG.width=32
AT91C_SYSC_SYSC_VREG.byteEndian=little
# ========== Register definition for AIC peripheral ========== 
AT91C_AIC_ICCR.name="AT91C_AIC_ICCR"
AT91C_AIC_ICCR.description="Interrupt Clear Command Register"
AT91C_AIC_ICCR.helpkey="Interrupt Clear Command Register"
AT91C_AIC_ICCR.access=memorymapped
AT91C_AIC_ICCR.address=0xFFFFF128
AT91C_AIC_ICCR.width=32
AT91C_AIC_ICCR.byteEndian=little
AT91C_AIC_ICCR.type=enum
AT91C_AIC_ICCR.enum.0.name=*** Write only ***
AT91C_AIC_ICCR.enum.1.name=Error
AT91C_AIC_IECR.name="AT91C_AIC_IECR"
AT91C_AIC_IECR.description="Interrupt Enable Command Register"
AT91C_AIC_IECR.helpkey="Interrupt Enable Command Register"
AT91C_AIC_IECR.access=memorymapped
AT91C_AIC_IECR.address=0xFFFFF120
AT91C_AIC_IECR.width=32
AT91C_AIC_IECR.byteEndian=little
AT91C_AIC_IECR.type=enum
AT91C_AIC_IECR.enum.0.name=*** Write only ***
AT91C_AIC_IECR.enum.1.name=Error
AT91C_AIC_SMR.name="AT91C_AIC_SMR"
AT91C_AIC_SMR.description="Source Mode Register"
AT91C_AIC_SMR.helpkey="Source Mode Register"
AT91C_AIC_SMR.access=memorymapped
AT91C_AIC_SMR.address=0xFFFFF000
AT91C_AIC_SMR.width=32
AT91C_AIC_SMR.byteEndian=little
AT91C_AIC_ISCR.name="AT91C_AIC_ISCR"
AT91C_AIC_ISCR.description="Interrupt Set Command Register"
AT91C_AIC_ISCR.helpkey="Interrupt Set Command Register"
AT91C_AIC_ISCR.access=memorymapped
AT91C_AIC_ISCR.address=0xFFFFF12C
AT91C_AIC_ISCR.width=32
AT91C_AIC_ISCR.byteEndian=little
AT91C_AIC_ISCR.type=enum
AT91C_AIC_ISCR.enum.0.name=*** Write only ***
AT91C_AIC_ISCR.enum.1.name=Error
AT91C_AIC_EOICR.name="AT91C_AIC_EOICR"
AT91C_AIC_EOICR.description="End of Interrupt Command Register"
AT91C_AIC_EOICR.helpkey="End of Interrupt Command Register"
AT91C_AIC_EOICR.access=memorymapped
AT91C_AIC_EOICR.address=0xFFFFF130
AT91C_AIC_EOICR.width=32
AT91C_AIC_EOICR.byteEndian=little
AT91C_AIC_EOICR.type=enum
AT91C_AIC_EOICR.enum.0.name=*** Write only ***
AT91C_AIC_EOICR.enum.1.name=Error
AT91C_AIC_DCR.name="AT91C_AIC_DCR"
AT91C_AIC_DCR.description="Debug Control Register (Protect)"
AT91C_AIC_DCR.helpkey="Debug Control Register (Protect)"
AT91C_AIC_DCR.access=memorymapped
AT91C_AIC_DCR.address=0xFFFFF138
AT91C_AIC_DCR.width=32
AT91C_AIC_DCR.byteEndian=little
AT91C_AIC_FFER.name="AT91C_AIC_FFER"
AT91C_AIC_FFER.description="Fast Forcing Enable Register"
AT91C_AIC_FFER.helpkey="Fast Forcing Enable Register"
AT91C_AIC_FFER.access=memorymapped
AT91C_AIC_FFER.address=0xFFFFF140
AT91C_AIC_FFER.width=32
AT91C_AIC_FFER.byteEndian=little
AT91C_AIC_FFER.type=enum
AT91C_AIC_FFER.enum.0.name=*** Write only ***
AT91C_AIC_FFER.enum.1.name=Error
AT91C_AIC_SVR.name="AT91C_AIC_SVR"
AT91C_AIC_SVR.description="Source Vector Register"
AT91C_AIC_SVR.helpkey="Source Vector Register"
AT91C_AIC_SVR.access=memorymapped
AT91C_AIC_SVR.address=0xFFFFF080
AT91C_AIC_SVR.width=32
AT91C_AIC_SVR.byteEndian=little
AT91C_AIC_SPU.name="AT91C_AIC_SPU"
AT91C_AIC_SPU.description="Spurious Vector Register"
AT91C_AIC_SPU.helpkey="Spurious Vector Register"
AT91C_AIC_SPU.access=memorymapped
AT91C_AIC_SPU.address=0xFFFFF134
AT91C_AIC_SPU.width=32
AT91C_AIC_SPU.byteEndian=little
AT91C_AIC_FFDR.name="AT91C_AIC_FFDR"
AT91C_AIC_FFDR.description="Fast Forcing Disable Register"
AT91C_AIC_FFDR.helpkey="Fast Forcing Disable Register"
AT91C_AIC_FFDR.access=memorymapped
AT91C_AIC_FFDR.address=0xFFFFF144
AT91C_AIC_FFDR.width=32
AT91C_AIC_FFDR.byteEndian=little
AT91C_AIC_FFDR.type=enum
AT91C_AIC_FFDR.enum.0.name=*** Write only ***
AT91C_AIC_FFDR.enum.1.name=Error
AT91C_AIC_FVR.name="AT91C_AIC_FVR"
AT91C_AIC_FVR.description="FIQ Vector Register"
AT91C_AIC_FVR.helpkey="FIQ Vector Register"
AT91C_AIC_FVR.access=memorymapped
AT91C_AIC_FVR.address=0xFFFFF104
AT91C_AIC_FVR.width=32
AT91C_AIC_FVR.byteEndian=little
AT91C_AIC_FVR.permission.write=none
AT91C_AIC_FFSR.name="AT91C_AIC_FFSR"
AT91C_AIC_FFSR.description="Fast Forcing Status Register"
AT91C_AIC_FFSR.helpkey="Fast Forcing Status Register"
AT91C_AIC_FFSR.access=memorymapped
AT91C_AIC_FFSR.address=0xFFFFF148
AT91C_AIC_FFSR.width=32
AT91C_AIC_FFSR.byteEndian=little
AT91C_AIC_FFSR.permission.write=none
AT91C_AIC_IMR.name="AT91C_AIC_IMR"
AT91C_AIC_IMR.description="Interrupt Mask Register"
AT91C_AIC_IMR.helpkey="Interrupt Mask Register"
AT91C_AIC_IMR.access=memorymapped
AT91C_AIC_IMR.address=0xFFFFF110
AT91C_AIC_IMR.width=32
AT91C_AIC_IMR.byteEndian=little
AT91C_AIC_IMR.permission.write=none
AT91C_AIC_ISR.name="AT91C_AIC_ISR"
AT91C_AIC_ISR.description="Interrupt Status Register"
AT91C_AIC_ISR.helpkey="Interrupt Status Register"
AT91C_AIC_ISR.access=memorymapped
AT91C_AIC_ISR.address=0xFFFFF108
AT91C_AIC_ISR.width=32
AT91C_AIC_ISR.byteEndian=little
AT91C_AIC_ISR.permission.write=none
AT91C_AIC_IVR.name="AT91C_AIC_IVR"
AT91C_AIC_IVR.description="IRQ Vector Register"
AT91C_AIC_IVR.helpkey="IRQ Vector Register"
AT91C_AIC_IVR.access=memorymapped
AT91C_AIC_IVR.address=0xFFFFF100
AT91C_AIC_IVR.width=32
AT91C_AIC_IVR.byteEndian=little
AT91C_AIC_IVR.permission.write=none
AT91C_AIC_IDCR.name="AT91C_AIC_IDCR"
AT91C_AIC_IDCR.description="Interrupt Disable Command Register"
AT91C_AIC_IDCR.helpkey="Interrupt Disable Command Register"
AT91C_AIC_IDCR.access=memorymapped
AT91C_AIC_IDCR.address=0xFFFFF124
AT91C_AIC_IDCR.width=32
AT91C_AIC_IDCR.byteEndian=little
AT91C_AIC_IDCR.type=enum
AT91C_AIC_IDCR.enum.0.name=*** Write only ***
AT91C_AIC_IDCR.enum.1.name=Error
AT91C_AIC_CISR.name="AT91C_AIC_CISR"
AT91C_AIC_CISR.description="Core Interrupt Status Register"
AT91C_AIC_CISR.helpkey="Core Interrupt Status Register"
AT91C_AIC_CISR.access=memorymapped
AT91C_AIC_CISR.address=0xFFFFF114
AT91C_AIC_CISR.width=32
AT91C_AIC_CISR.byteEndian=little
AT91C_AIC_CISR.permission.write=none
AT91C_AIC_IPR.name="AT91C_AIC_IPR"
AT91C_AIC_IPR.description="Interrupt Pending Register"
AT91C_AIC_IPR.helpkey="Interrupt Pending Register"
AT91C_AIC_IPR.access=memorymapped
AT91C_AIC_IPR.address=0xFFFFF10C
AT91C_AIC_IPR.width=32
AT91C_AIC_IPR.byteEndian=little
AT91C_AIC_IPR.permission.write=none
# ========== Register definition for DBGU peripheral ========== 
AT91C_DBGU_C2R.name="AT91C_DBGU_C2R"
AT91C_DBGU_C2R.description="Chip ID2 Register"
AT91C_DBGU_C2R.helpkey="Chip ID2 Register"
AT91C_DBGU_C2R.access=memorymapped
AT91C_DBGU_C2R.address=0xFFFFF244
AT91C_DBGU_C2R.width=32
AT91C_DBGU_C2R.byteEndian=little
AT91C_DBGU_C2R.permission.write=none
AT91C_DBGU_THR.name="AT91C_DBGU_THR"
AT91C_DBGU_THR.description="Transmitter Holding Register"
AT91C_DBGU_THR.helpkey="Transmitter Holding Register"
AT91C_DBGU_THR.access=memorymapped
AT91C_DBGU_THR.address=0xFFFFF21C
AT91C_DBGU_THR.width=32
AT91C_DBGU_THR.byteEndian=little
AT91C_DBGU_THR.type=enum
AT91C_DBGU_THR.enum.0.name=*** Write only ***
AT91C_DBGU_THR.enum.1.name=Error
AT91C_DBGU_CSR.name="AT91C_DBGU_CSR"
AT91C_DBGU_CSR.description="Channel Status Register"
AT91C_DBGU_CSR.helpkey="Channel Status Register"
AT91C_DBGU_CSR.access=memorymapped
AT91C_DBGU_CSR.address=0xFFFFF214
AT91C_DBGU_CSR.width=32
AT91C_DBGU_CSR.byteEndian=little
AT91C_DBGU_CSR.permission.write=none
AT91C_DBGU_IDR.name="AT91C_DBGU_IDR"
AT91C_DBGU_IDR.description="Interrupt Disable Register"
AT91C_DBGU_IDR.helpkey="Interrupt Disable Register"
AT91C_DBGU_IDR.access=memorymapped
AT91C_DBGU_IDR.address=0xFFFFF20C
AT91C_DBGU_IDR.width=32
AT91C_DBGU_IDR.byteEndian=little
AT91C_DBGU_IDR.type=enum
AT91C_DBGU_IDR.enum.0.name=*** Write only ***
AT91C_DBGU_IDR.enum.1.name=Error
AT91C_DBGU_MR.name="AT91C_DBGU_MR"
AT91C_DBGU_MR.description="Mode Register"
AT91C_DBGU_MR.helpkey="Mode Register"
AT91C_DBGU_MR.access=memorymapped
AT91C_DBGU_MR.address=0xFFFFF204
AT91C_DBGU_MR.width=32
AT91C_DBGU_MR.byteEndian=little
AT91C_DBGU_FNTR.name="AT91C_DBGU_FNTR"
AT91C_DBGU_FNTR.description="Force NTRST Register"
AT91C_DBGU_FNTR.helpkey="Force NTRST Register"
AT91C_DBGU_FNTR.access=memorymapped
AT91C_DBGU_FNTR.address=0xFFFFF248
AT91C_DBGU_FNTR.width=32
AT91C_DBGU_FNTR.byteEndian=little
AT91C_DBGU_C1R.name="AT91C_DBGU_C1R"
AT91C_DBGU_C1R.description="Chip ID1 Register"
AT91C_DBGU_C1R.helpkey="Chip ID1 Register"
AT91C_DBGU_C1R.access=memorymapped
AT91C_DBGU_C1R.address=0xFFFFF240
AT91C_DBGU_C1R.width=32
AT91C_DBGU_C1R.byteEndian=little
AT91C_DBGU_C1R.permission.write=none
AT91C_DBGU_BRGR.name="AT91C_DBGU_BRGR"
AT91C_DBGU_BRGR.description="Baud Rate Generator Register"
AT91C_DBGU_BRGR.helpkey="Baud Rate Generator Register"
AT91C_DBGU_BRGR.access=memorymapped
AT91C_DBGU_BRGR.address=0xFFFFF220
AT91C_DBGU_BRGR.width=32
AT91C_DBGU_BRGR.byteEndian=little
AT91C_DBGU_RHR.name="AT91C_DBGU_RHR"
AT91C_DBGU_RHR.description="Receiver Holding Register"
AT91C_DBGU_RHR.helpkey="Receiver Holding Register"
AT91C_DBGU_RHR.access=memorymapped
AT91C_DBGU_RHR.address=0xFFFFF218
AT91C_DBGU_RHR.width=32
AT91C_DBGU_RHR.byteEndian=little
AT91C_DBGU_RHR.permission.write=none
AT91C_DBGU_IMR.name="AT91C_DBGU_IMR"
AT91C_DBGU_IMR.description="Interrupt Mask Register"
AT91C_DBGU_IMR.helpkey="Interrupt Mask Register"
AT91C_DBGU_IMR.access=memorymapped
AT91C_DBGU_IMR.address=0xFFFFF210
AT91C_DBGU_IMR.width=32
AT91C_DBGU_IMR.byteEndian=little
AT91C_DBGU_IMR.permission.write=none
AT91C_DBGU_IER.name="AT91C_DBGU_IER"
AT91C_DBGU_IER.description="Interrupt Enable Register"
AT91C_DBGU_IER.helpkey="Interrupt Enable Register"
AT91C_DBGU_IER.access=memorymapped
AT91C_DBGU_IER.address=0xFFFFF208
AT91C_DBGU_IER.width=32
AT91C_DBGU_IER.byteEndian=little
AT91C_DBGU_IER.type=enum
AT91C_DBGU_IER.enum.0.name=*** Write only ***
AT91C_DBGU_IER.enum.1.name=Error
AT91C_DBGU_CR.name="AT91C_DBGU_CR"
AT91C_DBGU_CR.description="Control Register"
AT91C_DBGU_CR.helpkey="Control Register"
AT91C_DBGU_CR.access=memorymapped
AT91C_DBGU_CR.address=0xFFFFF200
AT91C_DBGU_CR.width=32
AT91C_DBGU_CR.byteEndian=little
AT91C_DBGU_CR.type=enum
AT91C_DBGU_CR.enum.0.name=*** Write only ***
AT91C_DBGU_CR.enum.1.name=Error
# ========== Register definition for PDC_DBGU peripheral ========== 
AT91C_DBGU_TNCR.name="AT91C_DBGU_TNCR"
AT91C_DBGU_TNCR.description="Transmit Next Counter Register"
AT91C_DBGU_TNCR.helpkey="Transmit Next Counter Register"
AT91C_DBGU_TNCR.access=memorymapped
AT91C_DBGU_TNCR.address=0xFFFFF31C
AT91C_DBGU_TNCR.width=32
AT91C_DBGU_TNCR.byteEndian=little
AT91C_DBGU_RNCR.name="AT91C_DBGU_RNCR"
AT91C_DBGU_RNCR.description="Receive Next Counter Register"
AT91C_DBGU_RNCR.helpkey="Receive Next Counter Register"
AT91C_DBGU_RNCR.access=memorymapped
AT91C_DBGU_RNCR.address=0xFFFFF314
AT91C_DBGU_RNCR.width=32
AT91C_DBGU_RNCR.byteEndian=little
AT91C_DBGU_PTCR.name="AT91C_DBGU_PTCR"
AT91C_DBGU_PTCR.description="PDC Transfer Control Register"
AT91C_DBGU_PTCR.helpkey="PDC Transfer Control Register"
AT91C_DBGU_PTCR.access=memorymapped
AT91C_DBGU_PTCR.address=0xFFFFF320
AT91C_DBGU_PTCR.width=32
AT91C_DBGU_PTCR.byteEndian=little
AT91C_DBGU_PTCR.type=enum
AT91C_DBGU_PTCR.enum.0.name=*** Write only ***
AT91C_DBGU_PTCR.enum.1.name=Error
AT91C_DBGU_PTSR.name="AT91C_DBGU_PTSR"
AT91C_DBGU_PTSR.description="PDC Transfer Status Register"
AT91C_DBGU_PTSR.helpkey="PDC Transfer Status Register"
AT91C_DBGU_PTSR.access=memorymapped
AT91C_DBGU_PTSR.address=0xFFFFF324
AT91C_DBGU_PTSR.width=32