📄 at91sam7s64.tcl
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# -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
set AT91C_SPI_CPOL [expr 0x1 << 0 ]
set AT91C_SPI_NCPHA [expr 0x1 << 1 ]
set AT91C_SPI_CSAAT [expr 0x1 << 2 ]
set AT91C_SPI_BITS [expr 0xF << 4 ]
set AT91C_SPI_BITS_8 [expr 0x0 << 4 ]
set AT91C_SPI_BITS_9 [expr 0x1 << 4 ]
set AT91C_SPI_BITS_10 [expr 0x2 << 4 ]
set AT91C_SPI_BITS_11 [expr 0x3 << 4 ]
set AT91C_SPI_BITS_12 [expr 0x4 << 4 ]
set AT91C_SPI_BITS_13 [expr 0x5 << 4 ]
set AT91C_SPI_BITS_14 [expr 0x6 << 4 ]
set AT91C_SPI_BITS_15 [expr 0x7 << 4 ]
set AT91C_SPI_BITS_16 [expr 0x8 << 4 ]
set AT91C_SPI_SCBR [expr 0xFF << 8 ]
set AT91C_SPI_DLYBS [expr 0xFF << 16 ]
set AT91C_SPI_DLYBCT [expr 0xFF << 24 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Analog to Digital Convertor
# *****************************************************************************
# -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
set AT91C_ADC_SWRST [expr 0x1 << 0 ]
set AT91C_ADC_START [expr 0x1 << 1 ]
# -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
set AT91C_ADC_TRGEN [expr 0x1 << 0 ]
set AT91C_ADC_TRGEN_DIS 0x0
set AT91C_ADC_TRGEN_EN 0x1
set AT91C_ADC_TRGSEL [expr 0x7 << 1 ]
set AT91C_ADC_TRGSEL_TIOA0 [expr 0x0 << 1 ]
set AT91C_ADC_TRGSEL_TIOA1 [expr 0x1 << 1 ]
set AT91C_ADC_TRGSEL_TIOA2 [expr 0x2 << 1 ]
set AT91C_ADC_TRGSEL_TIOA3 [expr 0x3 << 1 ]
set AT91C_ADC_TRGSEL_TIOA4 [expr 0x4 << 1 ]
set AT91C_ADC_TRGSEL_TIOA5 [expr 0x5 << 1 ]
set AT91C_ADC_TRGSEL_EXT [expr 0x6 << 1 ]
set AT91C_ADC_LOWRES [expr 0x1 << 4 ]
set AT91C_ADC_LOWRES_10_BIT [expr 0x0 << 4 ]
set AT91C_ADC_LOWRES_8_BIT [expr 0x1 << 4 ]
set AT91C_ADC_SLEEP [expr 0x1 << 5 ]
set AT91C_ADC_SLEEP_NORMAL_MODE [expr 0x0 << 5 ]
set AT91C_ADC_SLEEP_MODE [expr 0x1 << 5 ]
set AT91C_ADC_PRESCAL [expr 0x3F << 8 ]
set AT91C_ADC_STARTUP [expr 0x1F << 16 ]
set AT91C_ADC_SHTIM [expr 0xF << 24 ]
# -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
set AT91C_ADC_CH0 [expr 0x1 << 0 ]
set AT91C_ADC_CH1 [expr 0x1 << 1 ]
set AT91C_ADC_CH2 [expr 0x1 << 2 ]
set AT91C_ADC_CH3 [expr 0x1 << 3 ]
set AT91C_ADC_CH4 [expr 0x1 << 4 ]
set AT91C_ADC_CH5 [expr 0x1 << 5 ]
set AT91C_ADC_CH6 [expr 0x1 << 6 ]
set AT91C_ADC_CH7 [expr 0x1 << 7 ]
# -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
set AT91C_ADC_CH0 [expr 0x1 << 0 ]
set AT91C_ADC_CH1 [expr 0x1 << 1 ]
set AT91C_ADC_CH2 [expr 0x1 << 2 ]
set AT91C_ADC_CH3 [expr 0x1 << 3 ]
set AT91C_ADC_CH4 [expr 0x1 << 4 ]
set AT91C_ADC_CH5 [expr 0x1 << 5 ]
set AT91C_ADC_CH6 [expr 0x1 << 6 ]
set AT91C_ADC_CH7 [expr 0x1 << 7 ]
# -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
set AT91C_ADC_CH0 [expr 0x1 << 0 ]
set AT91C_ADC_CH1 [expr 0x1 << 1 ]
set AT91C_ADC_CH2 [expr 0x1 << 2 ]
set AT91C_ADC_CH3 [expr 0x1 << 3 ]
set AT91C_ADC_CH4 [expr 0x1 << 4 ]
set AT91C_ADC_CH5 [expr 0x1 << 5 ]
set AT91C_ADC_CH6 [expr 0x1 << 6 ]
set AT91C_ADC_CH7 [expr 0x1 << 7 ]
# -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
set AT91C_ADC_EOC0 [expr 0x1 << 0 ]
set AT91C_ADC_EOC1 [expr 0x1 << 1 ]
set AT91C_ADC_EOC2 [expr 0x1 << 2 ]
set AT91C_ADC_EOC3 [expr 0x1 << 3 ]
set AT91C_ADC_EOC4 [expr 0x1 << 4 ]
set AT91C_ADC_EOC5 [expr 0x1 << 5 ]
set AT91C_ADC_EOC6 [expr 0x1 << 6 ]
set AT91C_ADC_EOC7 [expr 0x1 << 7 ]
set AT91C_ADC_OVRE0 [expr 0x1 << 8 ]
set AT91C_ADC_OVRE1 [expr 0x1 << 9 ]
set AT91C_ADC_OVRE2 [expr 0x1 << 10 ]
set AT91C_ADC_OVRE3 [expr 0x1 << 11 ]
set AT91C_ADC_OVRE4 [expr 0x1 << 12 ]
set AT91C_ADC_OVRE5 [expr 0x1 << 13 ]
set AT91C_ADC_OVRE6 [expr 0x1 << 14 ]
set AT91C_ADC_OVRE7 [expr 0x1 << 15 ]
set AT91C_ADC_DRDY [expr 0x1 << 16 ]
set AT91C_ADC_GOVRE [expr 0x1 << 17 ]
set AT91C_ADC_ENDRX [expr 0x1 << 18 ]
set AT91C_ADC_RXBUFF [expr 0x1 << 19 ]
# -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
set AT91C_ADC_LDATA [expr 0x3FF << 0 ]
# -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
set AT91C_ADC_EOC0 [expr 0x1 << 0 ]
set AT91C_ADC_EOC1 [expr 0x1 << 1 ]
set AT91C_ADC_EOC2 [expr 0x1 << 2 ]
set AT91C_ADC_EOC3 [expr 0x1 << 3 ]
set AT91C_ADC_EOC4 [expr 0x1 << 4 ]
set AT91C_ADC_EOC5 [expr 0x1 << 5 ]
set AT91C_ADC_EOC6 [expr 0x1 << 6 ]
set AT91C_ADC_EOC7 [expr 0x1 << 7 ]
set AT91C_ADC_OVRE0 [expr 0x1 << 8 ]
set AT91C_ADC_OVRE1 [expr 0x1 << 9 ]
set AT91C_ADC_OVRE2 [expr 0x1 << 10 ]
set AT91C_ADC_OVRE3 [expr 0x1 << 11 ]
set AT91C_ADC_OVRE4 [expr 0x1 << 12 ]
set AT91C_ADC_OVRE5 [expr 0x1 << 13 ]
set AT91C_ADC_OVRE6 [expr 0x1 << 14 ]
set AT91C_ADC_OVRE7 [expr 0x1 << 15 ]
set AT91C_ADC_DRDY [expr 0x1 << 16 ]
set AT91C_ADC_GOVRE [expr 0x1 << 17 ]
set AT91C_ADC_ENDRX [expr 0x1 << 18 ]
set AT91C_ADC_RXBUFF [expr 0x1 << 19 ]
# -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
set AT91C_ADC_EOC0 [expr 0x1 << 0 ]
set AT91C_ADC_EOC1 [expr 0x1 << 1 ]
set AT91C_ADC_EOC2 [expr 0x1 << 2 ]
set AT91C_ADC_EOC3 [expr 0x1 << 3 ]
set AT91C_ADC_EOC4 [expr 0x1 << 4 ]
set AT91C_ADC_EOC5 [expr 0x1 << 5 ]
set AT91C_ADC_EOC6 [expr 0x1 << 6 ]
set AT91C_ADC_EOC7 [expr 0x1 << 7 ]
set AT91C_ADC_OVRE0 [expr 0x1 << 8 ]
set AT91C_ADC_OVRE1 [expr 0x1 << 9 ]
set AT91C_ADC_OVRE2 [expr 0x1 << 10 ]
set AT91C_ADC_OVRE3 [expr 0x1 << 11 ]
set AT91C_ADC_OVRE4 [expr 0x1 << 12 ]
set AT91C_ADC_OVRE5 [expr 0x1 << 13 ]
set AT91C_ADC_OVRE6 [expr 0x1 << 14 ]
set AT91C_ADC_OVRE7 [expr 0x1 << 15 ]
set AT91C_ADC_DRDY [expr 0x1 << 16 ]
set AT91C_ADC_GOVRE [expr 0x1 << 17 ]
set AT91C_ADC_ENDRX [expr 0x1 << 18 ]
set AT91C_ADC_RXBUFF [expr 0x1 << 19 ]
# -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
set AT91C_ADC_EOC0 [expr 0x1 << 0 ]
set AT91C_ADC_EOC1 [expr 0x1 << 1 ]
set AT91C_ADC_EOC2 [expr 0x1 << 2 ]
set AT91C_ADC_EOC3 [expr 0x1 << 3 ]
set AT91C_ADC_EOC4 [expr 0x1 << 4 ]
set AT91C_ADC_EOC5 [expr 0x1 << 5 ]
set AT91C_ADC_EOC6 [expr 0x1 << 6 ]
set AT91C_ADC_EOC7 [expr 0x1 << 7 ]
set AT91C_ADC_OVRE0 [expr 0x1 << 8 ]
set AT91C_ADC_OVRE1 [expr 0x1 << 9 ]
set AT91C_ADC_OVRE2 [expr 0x1 << 10 ]
set AT91C_ADC_OVRE3 [expr 0x1 << 11 ]
set AT91C_ADC_OVRE4 [expr 0x1 << 12 ]
set AT91C_ADC_OVRE5 [expr 0x1 << 13 ]
set AT91C_ADC_OVRE6 [expr 0x1 << 14 ]
set AT91C_ADC_OVRE7 [expr 0x1 << 15 ]
set AT91C_ADC_DRDY [expr 0x1 << 16 ]
set AT91C_ADC_GOVRE [expr 0x1 << 17 ]
set AT91C_ADC_ENDRX [expr 0x1 << 18 ]
set AT91C_ADC_RXBUFF [expr 0x1 << 19 ]
# -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
set AT91C_ADC_DATA [expr 0x3FF << 0 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
# *****************************************************************************
# -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
set AT91C_SSC_RXEN [expr 0x1 << 0 ]
set AT91C_SSC_RXDIS [expr 0x1 << 1 ]
set AT91C_SSC_TXEN [expr 0x1 << 8 ]
set AT91C_SSC_TXDIS [expr 0x1 << 9 ]
set AT91C_SSC_SWRST [expr 0x1 << 15 ]
# -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
set AT91C_SSC_CKS [expr 0x3 << 0 ]
set AT91C_SSC_CKS_DIV 0x0
set AT91C_SSC_CKS_TK 0x1
set AT91C_SSC_CKS_RK 0x2
set AT91C_SSC_CKO [expr 0x7 << 2 ]
set AT91C_SSC_CKO_NONE [expr 0x0 << 2 ]
set AT91C_SSC_CKO_CONTINOUS [expr 0x1 << 2 ]
set AT91C_SSC_CKO_DATA_TX [expr 0x2 << 2 ]
set AT91C_SSC_CKI [expr 0x1 << 5 ]
set AT91C_SSC_CKG [expr 0x3 << 6 ]
set AT91C_SSC_CKG_NONE [expr 0x0 << 6 ]
set AT91C_SSC_CKG_LOW [expr 0x1 << 6 ]
set AT91C_SSC_CKG_HIGH [expr 0x2 << 6 ]
set AT91C_SSC_START [expr 0xF << 8 ]
set AT91C_SSC_START_CONTINOUS [expr 0x0 << 8 ]
set AT91C_SSC_START_TX [expr 0x1 << 8 ]
set AT91C_SSC_START_LOW_RF [expr 0x2 << 8 ]
set AT91C_SSC_START_HIGH_RF [expr 0x3 << 8 ]
set AT91C_SSC_START_FALL_RF [expr 0x4 << 8 ]
set AT91C_SSC_START_RISE_RF [expr 0x5 << 8 ]
set AT91C_SSC_START_LEVEL_RF [expr 0x6 << 8 ]
set AT91C_SSC_START_EDGE_RF [expr 0x7 << 8 ]
set AT91C_SSC_START_0 [expr 0x8 << 8 ]
set AT91C_SSC_STOP [expr 0x1 << 12 ]
set AT91C_SSC_STTOUT [expr 0x1 << 15 ]
set AT91C_SSC_STTDLY [expr 0xFF << 16 ]
set AT91C_SSC_PERIOD [expr 0xFF << 24 ]
# -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
set AT91C_SSC_DATLEN [expr 0x1F << 0 ]
set AT91C_SSC_LOOP [expr 0x1 << 5 ]
set AT91C_SSC_MSBF [expr 0x1 << 7 ]
set AT91C_SSC_DATNB [expr 0xF << 8 ]
set AT91C_SSC_FSLEN [expr 0xF << 16 ]
set AT91C_SSC_FSOS [expr 0x7 << 20 ]
set AT91C_SSC_FSOS_NONE [expr 0x0 << 20 ]
set AT91C_SSC_FSOS_NEGATIVE [expr 0x1 << 20 ]
set AT91C_SSC_FSOS_POSITIVE [expr 0x2 << 20 ]
set AT91C_SSC_FSOS_LOW [expr 0x3 << 20 ]
set AT91C_SSC_FSOS_HIGH [expr 0x4 << 20 ]
set AT91C_SSC_FSOS_TOGGLE [expr 0x5 << 20 ]
set AT91C_SSC_FSEDGE [expr 0x1 << 24 ]
# -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
set AT91C_SSC_CKS [expr 0x3 << 0 ]
set AT91C_SSC_CKS_DIV 0x0
set AT91C_SSC_CKS_TK 0x1
set AT91C_SSC_CKS_RK 0x2
set AT91C_SSC_CKO [expr 0x7 << 2 ]
set AT91C_SSC_CKO_NONE [expr 0x0 << 2 ]
set AT91C_SSC_CKO_CONTINOUS [expr 0x1 << 2 ]
set AT91C_SSC_CKO_DATA_TX [expr 0x2 << 2 ]
set AT91C_SSC_CKI [expr 0x1 << 5 ]
set AT91C_SSC_CKG [expr 0x3 << 6 ]
set AT91C_SSC_CKG_NONE [expr 0x0 << 6 ]
set AT91C_SSC_CKG_LOW [expr 0x1 << 6 ]
set AT91C_SSC_CKG_HIGH [expr 0x2 << 6 ]
set AT91C_SSC_START [expr 0xF << 8 ]
set AT91C_SSC_START_CONTINOUS [expr 0x0 << 8 ]
set AT91C_SSC_START_TX [expr 0x1 << 8 ]
set AT91C_SSC_START_LOW_RF [expr 0x2 << 8 ]
set AT91C_SSC_START_HIGH_RF [expr 0x3 << 8 ]
set AT91C_SSC_START_FALL_RF [expr 0x4 << 8 ]
set AT91C_SSC_START_RISE_RF [expr 0x5 << 8 ]
set AT91C_SSC_START_LEVEL_RF [expr 0x6 << 8 ]
set AT91C_SSC_START_EDGE_RF [expr 0x7 << 8 ]
set AT91C_SSC_START_0 [expr 0x8 << 8 ]
set AT91C_SSC_STTOUT [expr 0x1 << 15 ]
set AT91C_SSC_STTDLY [expr 0xFF << 16 ]
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