📄 at91sam7s64.inc
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SPI_TPR # 4 ;- Transmit Pointer Register
SPI_TCR # 4 ;- Transmit Counter Register
SPI_RNPR # 4 ;- Receive Next Pointer Register
SPI_RNCR # 4 ;- Receive Next Counter Register
SPI_TNPR # 4 ;- Transmit Next Pointer Register
SPI_TNCR # 4 ;- Transmit Next Counter Register
SPI_PTCR # 4 ;- PDC Transfer Control Register
SPI_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable
AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable
AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset
AT91C_SPI_LASTXFER EQU (0x1:SHL:24) ;- (SPI) SPI Last Transfer
;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode
AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select
AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select
AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select
AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode
AT91C_SPI_FDIV EQU (0x1:SHL:3) ;- (SPI) Clock Selection
AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection
AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection
AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select
AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects
;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data
AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data
AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
;- -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full
AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty
AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error
AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status
AT91C_SPI_ENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer
AT91C_SPI_ENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer
AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt
AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt
AT91C_SPI_NSSR EQU (0x1:SHL:8) ;- (SPI) NSSR Interrupt
AT91C_SPI_TXEMPTY EQU (0x1:SHL:9) ;- (SPI) TXEMPTY Interrupt
AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status
;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity
AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase
AT91C_SPI_CSAAT EQU (0x1:SHL:2) ;- (SPI) Chip Select Active After Transfer
AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer
AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer
AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer
AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer
AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer
AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer
AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer
AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer
AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer
AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer
AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate
AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate
AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Analog to Digital Convertor
;- *****************************************************************************
^ 0 ;- AT91S_ADC
ADC_CR # 4 ;- ADC Control Register
ADC_MR # 4 ;- ADC Mode Register
# 8 ;- Reserved
ADC_CHER # 4 ;- ADC Channel Enable Register
ADC_CHDR # 4 ;- ADC Channel Disable Register
ADC_CHSR # 4 ;- ADC Channel Status Register
ADC_SR # 4 ;- ADC Status Register
ADC_LCDR # 4 ;- ADC Last Converted Data Register
ADC_IER # 4 ;- ADC Interrupt Enable Register
ADC_IDR # 4 ;- ADC Interrupt Disable Register
ADC_IMR # 4 ;- ADC Interrupt Mask Register
ADC_CDR0 # 4 ;- ADC Channel Data Register 0
ADC_CDR1 # 4 ;- ADC Channel Data Register 1
ADC_CDR2 # 4 ;- ADC Channel Data Register 2
ADC_CDR3 # 4 ;- ADC Channel Data Register 3
ADC_CDR4 # 4 ;- ADC Channel Data Register 4
ADC_CDR5 # 4 ;- ADC Channel Data Register 5
ADC_CDR6 # 4 ;- ADC Channel Data Register 6
ADC_CDR7 # 4 ;- ADC Channel Data Register 7
# 176 ;- Reserved
ADC_RPR # 4 ;- Receive Pointer Register
ADC_RCR # 4 ;- Receive Counter Register
ADC_TPR # 4 ;- Transmit Pointer Register
ADC_TCR # 4 ;- Transmit Counter Register
ADC_RNPR # 4 ;- Receive Next Pointer Register
ADC_RNCR # 4 ;- Receive Next Counter Register
ADC_TNPR # 4 ;- Transmit Next Pointer Register
ADC_TNCR # 4 ;- Transmit Next Counter Register
ADC_PTCR # 4 ;- PDC Transfer Control Register
ADC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
AT91C_ADC_SWRST EQU (0x1:SHL:0) ;- (ADC) Software Reset
AT91C_ADC_START EQU (0x1:SHL:1) ;- (ADC) Start Conversion
;- -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
AT91C_ADC_TRGEN EQU (0x1:SHL:0) ;- (ADC) Trigger Enable
AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
AT91C_ADC_TRGSEL EQU (0x7:SHL:1) ;- (ADC) Trigger Selection
AT91C_ADC_TRGSEL_TIOA0 EQU (0x0:SHL:1) ;- (ADC) Selected TRGSEL = TIAO0
AT91C_ADC_TRGSEL_TIOA1 EQU (0x1:SHL:1) ;- (ADC) Selected TRGSEL = TIAO1
AT91C_ADC_TRGSEL_TIOA2 EQU (0x2:SHL:1) ;- (ADC) Selected TRGSEL = TIAO2
AT91C_ADC_TRGSEL_TIOA3 EQU (0x3:SHL:1) ;- (ADC) Selected TRGSEL = TIAO3
AT91C_ADC_TRGSEL_TIOA4 EQU (0x4:SHL:1) ;- (ADC) Selected TRGSEL = TIAO4
AT91C_ADC_TRGSEL_TIOA5 EQU (0x5:SHL:1) ;- (ADC) Selected TRGSEL = TIAO5
AT91C_ADC_TRGSEL_EXT EQU (0x6:SHL:1) ;- (ADC) Selected TRGSEL = External Trigger
AT91C_ADC_LOWRES EQU (0x1:SHL:4) ;- (ADC) Resolution.
AT91C_ADC_LOWRES_10_BIT EQU (0x0:SHL:4) ;- (ADC) 10-bit resolution
AT91C_ADC_LOWRES_8_BIT EQU (0x1:SHL:4) ;- (ADC) 8-bit resolution
AT91C_ADC_SLEEP EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0:SHL:5) ;- (ADC) Normal Mode
AT91C_ADC_SLEEP_MODE EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
AT91C_ADC_PRESCAL EQU (0x3F:SHL:8) ;- (ADC) Prescaler rate selection
AT91C_ADC_STARTUP EQU (0x1F:SHL:16) ;- (ADC) Startup Time
AT91C_ADC_SHTIM EQU (0xF:SHL:24) ;- (ADC) Sample & Hold Time
;- -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
AT91C_ADC_CH0 EQU (0x1:SHL:0) ;- (ADC) Channel 0
AT91C_ADC_CH1 EQU (0x1:SHL:1) ;- (ADC) Channel 1
AT91C_ADC_CH2 EQU (0x1:SHL:2) ;- (ADC) Channel 2
AT91C_ADC_CH3 EQU (0x1:SHL:3) ;- (ADC) Channel 3
AT91C_ADC_CH4 EQU (0x1:SHL:4) ;- (ADC) Channel 4
AT91C_ADC_CH5 EQU (0x1:SHL:5) ;- (ADC) Channel 5
AT91C_ADC_CH6 EQU (0x1:SHL:6) ;- (ADC) Channel 6
AT91C_ADC_CH7 EQU (0x1:SHL:7) ;- (ADC) Channel 7
;- -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
;- -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
;- -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
AT91C_ADC_EOC0 EQU (0x1:SHL:0) ;- (ADC) End of Conversion
AT91C_ADC_EOC1 EQU (0x1:SHL:1) ;- (ADC) End of Conversion
AT91C_ADC_EOC2 EQU (0x1:SHL:2) ;- (ADC) End of Conversion
AT91C_ADC_EOC3 EQU (0x1:SHL:3) ;- (ADC) End of Conversion
AT91C_ADC_EOC4 EQU (0x1:SHL:4) ;- (ADC) End of Conversion
AT91C_ADC_EOC5 EQU (0x1:SHL:5) ;- (ADC) End of Conversion
AT91C_ADC_EOC6 EQU (0x1:SHL:6) ;- (ADC) End of Conversion
AT91C_ADC_EOC7 EQU (0x1:SHL:7) ;- (ADC) End of Conversion
AT91C_ADC_OVRE0 EQU (0x1:SHL:8) ;- (ADC) Overrun Error
AT91C_ADC_OVRE1 EQU (0x1:SHL:9) ;- (ADC) Overrun Error
AT91C_ADC_OVRE2 EQU (0x1:SHL:10) ;- (ADC) Overrun Error
AT91C_ADC_OVRE3 EQU (0x1:SHL:11) ;- (ADC) Overrun Error
AT91C_ADC_OVRE4 EQU (0x1:SHL:12) ;- (ADC) Overrun Error
AT91C_ADC_OVRE5 EQU (0x1:SHL:13) ;- (ADC) Overrun Error
AT91C_ADC_OVRE6 EQU (0x1:SHL:14) ;- (ADC) Overrun Error
AT91C_ADC_OVRE7 EQU (0x1:SHL:15) ;- (ADC) Overrun Error
AT91C_ADC_DRDY EQU (0x1:SHL:16) ;- (ADC) Data Ready
AT91C_ADC_GOVRE EQU (0x1:SHL:17) ;- (ADC) General Overrun
AT91C_ADC_ENDRX EQU (0x1:SHL:18) ;- (ADC) End of Receiver Transfer
AT91C_ADC_RXBUFF EQU (0x1:SHL:19) ;- (ADC) RXBUFF Interrupt
;- -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
AT91C_ADC_LDATA EQU (0x3FF:SHL:0) ;- (ADC) Last Data Converted
;- -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
;- -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
;- -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
;- -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
AT91C_ADC_DATA EQU (0x3FF:SHL:0) ;- (ADC) Converted Data
;- -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
;- -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
;- -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
;- -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
;- -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
;- -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
;- -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_SSC
SSC_CR # 4 ;- Control Register
SSC_CMR # 4 ;- Clock Mode Register
# 8 ;- Reserved
SSC_RCMR # 4 ;- Receive Clock ModeRegister
SSC_RFMR # 4 ;- Receive Frame Mode Register
SSC_TCMR # 4 ;- Transmit Clock Mode Register
SSC_TFMR # 4 ;- Transmit Frame Mode Register
SSC_RHR # 4 ;- Receive Holding Register
SSC_THR # 4 ;- Transmit Holding Register
# 8 ;- Reserved
SSC_RSHR # 4 ;- Receive Sync Holding Register
SSC_TSHR # 4 ;- Transmit Sync Holding Register
SSC_RC0R # 4 ;- Receive Compare 0 Register
SSC_RC1R # 4 ;- Receive Compare 1 Register
SSC_SR # 4 ;- Status Register
SSC_IER # 4 ;- Interrupt Enable Register
SSC_IDR # 4 ;- Interrupt Disable Register
SSC_IMR # 4 ;- Interrupt Mask Register
# 176 ;- Reserved
SSC_RPR # 4 ;- Receive Pointer Register
SSC_RCR # 4 ;- Receive Counter Register
SSC_TPR # 4 ;- Transmit Pointer Register
SSC_TCR # 4 ;- Transmit Counter Register
SSC_RNPR # 4 ;- Receive Next Pointer Register
SSC_RNCR # 4 ;- Receive Next Counter Register
SSC_TNPR # 4 ;- Transmit Next Pointer Register
SSC_TNCR # 4 ;- Transmit Next Counter Register
SSC_PTCR # 4 ;- PDC Transfer Control Register
SSC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
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