📄 at91sam7s64.inc
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AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32
AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64
;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask
AT91C_PMC_LOCK EQU (0x1:SHL:2) ;- (PMC) PLL Status/Enable/Disable/Mask
AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Reset Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_RSTC
RSTC_RCR # 4 ;- Reset Control Register
RSTC_RSR # 4 ;- Reset Status Register
RSTC_RMR # 4 ;- Reset Mode Register
;- -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
AT91C_SYSC_PROCRST EQU (0x1:SHL:0) ;- (RSTC) Processor Reset
AT91C_SYSC_ICERST EQU (0x1:SHL:1) ;- (RSTC) ICE Interface Reset
AT91C_SYSC_PERRST EQU (0x1:SHL:2) ;- (RSTC) Peripheral Reset
AT91C_SYSC_EXTRST EQU (0x1:SHL:3) ;- (RSTC) External Reset
AT91C_SYSC_KEY EQU (0xFF:SHL:24) ;- (RSTC) Password
;- -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
AT91C_SYSC_URSTS EQU (0x1:SHL:0) ;- (RSTC) User Reset Status
AT91C_SYSC_BODSTS EQU (0x1:SHL:1) ;- (RSTC) Brown-out Detection Status
AT91C_SYSC_RSTTYP EQU (0x7:SHL:8) ;- (RSTC) Reset Type
AT91C_SYSC_RSTTYP_POWERUP EQU (0x0:SHL:8) ;- (RSTC) Power-up Reset. VDDCORE rising.
AT91C_SYSC_RSTTYP_WATCHDOG EQU (0x2:SHL:8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
AT91C_SYSC_RSTTYP_SOFTWARE EQU (0x3:SHL:8) ;- (RSTC) Software Reset. Processor reset required by the software.
AT91C_SYSC_RSTTYP_USER EQU (0x4:SHL:8) ;- (RSTC) User Reset. NRST pin detected low.
AT91C_SYSC_RSTTYP_BROWNOUT EQU (0x5:SHL:8) ;- (RSTC) Brown-out Reset.
AT91C_SYSC_NRSTL EQU (0x1:SHL:16) ;- (RSTC) NRST pin level
AT91C_SYSC_SRCMP EQU (0x1:SHL:17) ;- (RSTC) Software Reset Command in Progress.
;- -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
AT91C_SYSC_URSTEN EQU (0x1:SHL:0) ;- (RSTC) User Reset Enable
AT91C_SYSC_URSTIEN EQU (0x1:SHL:4) ;- (RSTC) User Reset Interrupt Enable
AT91C_SYSC_ERSTL EQU (0xF:SHL:8) ;- (RSTC) User Reset Enable
AT91C_SYSC_BODIEN EQU (0x1:SHL:16) ;- (RSTC) Brown-out Detection Interrupt Enable
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_RTTC
RTTC_RTMR # 4 ;- Real-time Mode Register
RTTC_RTAR # 4 ;- Real-time Alarm Register
RTTC_RTVR # 4 ;- Real-time Value Register
RTTC_RTSR # 4 ;- Real-time Status Register
;- -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
AT91C_SYSC_RTPRES EQU (0xFFFF:SHL:0) ;- (RTTC) Real-time Timer Prescaler Value
AT91C_SYSC_ALMIEN EQU (0x1:SHL:16) ;- (RTTC) Alarm Interrupt Enable
AT91C_SYSC_RTTINCIEN EQU (0x1:SHL:17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
AT91C_SYSC_RTTRST EQU (0x1:SHL:18) ;- (RTTC) Real Time Timer Restart
;- -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
AT91C_SYSC_ALMV EQU (0x0:SHL:0) ;- (RTTC) Alarm Value
;- -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
AT91C_SYSC_CRTV EQU (0x0:SHL:0) ;- (RTTC) Current Real-time Value
;- -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
AT91C_SYSC_ALMS EQU (0x1:SHL:0) ;- (RTTC) Real-time Alarm Status
AT91C_SYSC_RTTINC EQU (0x1:SHL:1) ;- (RTTC) Real-time Timer Increment
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_PITC
PITC_PIMR # 4 ;- Period Interval Mode Register
PITC_PISR # 4 ;- Period Interval Status Register
PITC_PIVR # 4 ;- Period Interval Value Register
PITC_PIIR # 4 ;- Period Interval Image Register
;- -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
AT91C_SYSC_PIV EQU (0xFFFFF:SHL:0) ;- (PITC) Periodic Interval Value
AT91C_SYSC_PITEN EQU (0x1:SHL:24) ;- (PITC) Periodic Interval Timer Enabled
AT91C_SYSC_PITIEN EQU (0x1:SHL:25) ;- (PITC) Periodic Interval Timer Interrupt Enable
;- -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
AT91C_SYSC_PITS EQU (0x1:SHL:0) ;- (PITC) Periodic Interval Timer Status
;- -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
AT91C_SYSC_CPIV EQU (0xFFFFF:SHL:0) ;- (PITC) Current Periodic Interval Value
AT91C_SYSC_PICNT EQU (0xFFF:SHL:20) ;- (PITC) Periodic Interval Counter
;- -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_WDTC
WDTC_WDCR # 4 ;- Watchdog Control Register
WDTC_WDMR # 4 ;- Watchdog Mode Register
WDTC_WDSR # 4 ;- Watchdog Status Register
;- -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
AT91C_SYSC_WDRSTT EQU (0x1:SHL:0) ;- (WDTC) Watchdog Restart
;- -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
AT91C_SYSC_WDV EQU (0xFFF:SHL:0) ;- (WDTC) Watchdog Timer Restart
AT91C_SYSC_WDFIEN EQU (0x1:SHL:12) ;- (WDTC) Watchdog Fault Interrupt Enable
AT91C_SYSC_WDRSTEN EQU (0x1:SHL:13) ;- (WDTC) Watchdog Reset Enable
AT91C_SYSC_WDRPROC EQU (0x1:SHL:14) ;- (WDTC) Watchdog Timer Restart
AT91C_SYSC_WDDIS EQU (0x1:SHL:15) ;- (WDTC) Watchdog Disable
AT91C_SYSC_WDD EQU (0xFFF:SHL:16) ;- (WDTC) Watchdog Delta Value
AT91C_SYSC_WDDBGHLT EQU (0x1:SHL:28) ;- (WDTC) Watchdog Debug Halt
AT91C_SYSC_WDIDLEHLT EQU (0x1:SHL:29) ;- (WDTC) Watchdog Idle Halt
;- -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
AT91C_SYSC_WDUNF EQU (0x1:SHL:0) ;- (WDTC) Watchdog Underflow
AT91C_SYSC_WDERR EQU (0x1:SHL:1) ;- (WDTC) Watchdog Error
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Memory Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_MC
MC_RCR # 4 ;- MC Remap Control Register
MC_ASR # 4 ;- MC Abort Status Register
MC_AASR # 4 ;- MC Abort Address Status Register
# 84 ;- Reserved
MC_FMR # 4 ;- MC Flash Mode Register
MC_FCR # 4 ;- MC Flash Command Register
MC_FSR # 4 ;- MC Flash Status Register
;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status
AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte
AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word
AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word
AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status
AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read
AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write
AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch
AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
;- -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
AT91C_MC_FRDY EQU (0x1:SHL:0) ;- (MC) Flash Ready
AT91C_MC_LOCKE EQU (0x1:SHL:2) ;- (MC) Lock Error
AT91C_MC_PROGE EQU (0x1:SHL:3) ;- (MC) Programming Error
AT91C_MC_NEBP EQU (0x1:SHL:7) ;- (MC) No Erase Before Programming
AT91C_MC_FWS EQU (0x3:SHL:8) ;- (MC) Flash Wait State
AT91C_MC_FWS_0FWS EQU (0x0:SHL:8) ;- (MC) 1 cycle for Read, 2 for Write operations
AT91C_MC_FWS_1FWS EQU (0x1:SHL:8) ;- (MC) 2 cycles for Read, 3 for Write operations
AT91C_MC_FWS_2FWS EQU (0x2:SHL:8) ;- (MC) 3 cycles for Read, 4 for Write operations
AT91C_MC_FWS_3FWS EQU (0x3:SHL:8) ;- (MC) 4 cycles for Read, 4 for Write operations
AT91C_MC_FMCN EQU (0xFF:SHL:16) ;- (MC) Flash Microsecond Cycle Number
;- -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
AT91C_MC_FCMD EQU (0xF:SHL:0) ;- (MC) Flash Command
AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
AT91C_MC_PAGEN EQU (0x3FF:SHL:8) ;- (MC) Page Number
AT91C_MC_KEY EQU (0xFF:SHL:24) ;- (MC) Writing Protect Key
;- -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
AT91C_MC_SECURITY EQU (0x1:SHL:4) ;- (MC) Security Bit Status
AT91C_MC_GPNVM0 EQU (0x1:SHL:8) ;- (MC) Sector 0 Lock Status
AT91C_MC_GPNVM1 EQU (0x1:SHL:9) ;- (MC) Sector 1 Lock Status
AT91C_MC_GPNVM2 EQU (0x1:SHL:10) ;- (MC) Sector 2 Lock Status
AT91C_MC_GPNVM3 EQU (0x1:SHL:11) ;- (MC) Sector 3 Lock Status
AT91C_MC_GPNVM4 EQU (0x1:SHL:12) ;- (MC) Sector 4 Lock Status
AT91C_MC_GPNVM5 EQU (0x1:SHL:13) ;- (MC) Sector 5 Lock Status
AT91C_MC_GPNVM6 EQU (0x1:SHL:14) ;- (MC) Sector 6 Lock Status
AT91C_MC_GPNVM7 EQU (0x1:SHL:15) ;- (MC) Sector 7 Lock Status
AT91C_MC_LOCKS0 EQU (0x1:SHL:16) ;- (MC) Sector 0 Lock Status
AT91C_MC_LOCKS1 EQU (0x1:SHL:17) ;- (MC) Sector 1 Lock Status
AT91C_MC_LOCKS2 EQU (0x1:SHL:18) ;- (MC) Sector 2 Lock Status
AT91C_MC_LOCKS3 EQU (0x1:SHL:19) ;- (MC) Sector 3 Lock Status
AT91C_MC_LOCKS4 EQU (0x1:SHL:20) ;- (MC) Sector 4 Lock Status
AT91C_MC_LOCKS5 EQU (0x1:SHL:21) ;- (MC) Sector 5 Lock Status
AT91C_MC_LOCKS6 EQU (0x1:SHL:22) ;- (MC) Sector 6 Lock Status
AT91C_MC_LOCKS7 EQU (0x1:SHL:23) ;- (MC) Sector 7 Lock Status
AT91C_MC_LOCKS8 EQU (0x1:SHL:24) ;- (MC) Sector 8 Lock Status
AT91C_MC_LOCKS9 EQU (0x1:SHL:25) ;- (MC) Sector 9 Lock Status
AT91C_MC_LOCKS10 EQU (0x1:SHL:26) ;- (MC) Sector 10 Lock Status
AT91C_MC_LOCKS11 EQU (0x1:SHL:27) ;- (MC) Sector 11 Lock Status
AT91C_MC_LOCKS12 EQU (0x1:SHL:28) ;- (MC) Sector 12 Lock Status
AT91C_MC_LOCKS13 EQU (0x1:SHL:29) ;- (MC) Sector 13 Lock Status
AT91C_MC_LOCKS14 EQU (0x1:SHL:30) ;- (MC) Sector 14 Lock Status
AT91C_MC_LOCKS15 EQU (0x1:SHL:31) ;- (MC) Sector 15 Lock Status
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Serial Parallel Interface
;- *****************************************************************************
^ 0 ;- AT91S_SPI
SPI_CR # 4 ;- Control Register
SPI_MR # 4 ;- Mode Register
SPI_RDR # 4 ;- Receive Data Register
SPI_TDR # 4 ;- Transmit Data Register
SPI_SR # 4 ;- Status Register
SPI_IER # 4 ;- Interrupt Enable Register
SPI_IDR # 4 ;- Interrupt Disable Register
SPI_IMR # 4 ;- Interrupt Mask Register
# 16 ;- Reserved
SPI_CSR # 16 ;- Chip Select Register
# 192 ;- Reserved
SPI_RPR # 4 ;- Receive Pointer Register
SPI_RCR # 4 ;- Receive Counter Register
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