scc.h

这是一个uC/OS-II For cs8900的移植项目源代码．可以在uCOSV252.exe上运行

/******************************************************************************
* Filename     : scc.h                                                        *
* Program      : loader.                                                      *
* Copyright    : Copyright (C) 2001, Young-Su, Ahn.                           *
* Author       : Young-Su, Ahn <[e-mail]>                           *
* Description  : Header file for scc.c.                                       *
* Created at   : Wed Mar 13 2001.                                             *
* Based on     : pptboot-0.5.3, CS8900A device driver.                        *
* Modified by  :                                                              *
* Modified at  :                                                              *
******************************************************************************/
/* This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _SCC_H_42342134324234
#define _SCC_H_42342134324234

#include "main.h"

// 傈开函荐 荤侩啊瓷窍搁 荤侩且 抗沥.... (ば.ば).
typedef struct {
	union {
		ushort	io_rtx_data16;	// data read and write (4 bytes 傍埃).
		ulong	io_rtx_data32;
	} _BUF1;
	ushort		io_txcmd;				// transmit command (0144h).
	ushort		io_txlen;				// transmit data length (0146h).
	ushort		io_int;					// Interrupt Status Queue (0120h).
	ushort		io_ppptr;				// Packet Page Pointer.
	union {
		ushort	io_ppdata16;	// Packet Page Data (16 bits).
		ulong	io_ppdata32;	// Packet Page Data (32 bits).
	} _BUF2;
} ETH_IO_MAP;


// IO Mapped Packet Page.
//#define	IO_BASE			0x08000300 //HYPER
#define	IO_BASE			0x10000300       //EZBoard
#define IO_RTX_DATA		*((volatile short *)(IO_BASE + 0x00000000))	// RTx data.
#define IO_TXCMD		*((volatile short *)(IO_BASE + 0x00000004))	// RTx command.
#define IO_TXLEN		*((volatile short *)(IO_BASE + 0x00000006))	// transmit length.
#define IO_ISQ			*((volatile short *)(IO_BASE + 0x00000008))	// interrupt.
#define IO_PPPTR		*((volatile short *)(IO_BASE + 0x0000000a))	// packet page point.
#define IO_PPDATA		*((volatile short *)(IO_BASE + 0x0000000c))	// packet page data.

/*
bool	EthInit();					// Initialize the device.
bool	EthTx(void *pkt, int len);	// Send a packet.
bool	EthRx(void *pkt);			// Check for received packets.
void	EthHalt(void);				// stop SCC.
void	EthRestart(void);			// restart scc.
*/
///////////////////////////////////////////////////////////////////////////////
//                                                                           //
//                                                                           //
//                                                                           //
//                                                                           //
///////////////////////////////////////////////////////////////////////////////

// ID.
#define PP_ChipID					0x0000	// First Chip ID.  CS8900A : 0x630E
#define PP_ChipID2					0x0002	// Second Chip ID. CS8900A : 0x0800

#define PP_ISAIOB					0x0020	//  IO base address
#define PP_CS8900_ISAINT			0x0022	//  ISA interrupt select
#define PP_CS8920_ISAINT			0x0370	//  ISA interrupt select
#define PP_CS8900_ISADMA			0x0024	//  ISA Rec DMA channel
#define PP_CS8920_ISADMA			0x0374	//  ISA Rec DMA channel
#define PP_ISASOF					0x0026	//  ISA DMA offset
#define PP_DmaFrameCnt				0x0028	//  ISA DMA Frame count
#define PP_DmaByteCnt				0x002A	//  ISA DMA Byte count
#define PP_CS8900_ISAMemB			0x002C	//  Memory base
#define PP_CS8920_ISAMemB			0x0348	// 

#define PP_ISABootBase				0x0030	//  Boot Prom base 
#define PP_ISABootMask				0x0034	//  Boot Prom Mask

// EEPROM data and command registers.
#define PP_EECMD					0x0040	//  NVR Interface Command register
#define PP_EEData					0x0042	//  NVR Interface Data Register
#define PP_DebugReg					0x0044	//  Debug Register

#define PP_RxCFG					0x0102	//  Rx Bus config
#define PP_RxCTL					0x0104	//  Receive Control Register
#define PP_TxCFG					0x0106	//  Transmit Config Register
#define PP_TxCMD					0x0108	//  Transmit Command Register
#define PP_BufCFG					0x010A	//  Bus configuration Register
#define PP_LineCTL					0x0112	//  Line Config Register
#define PP_SelfCTL					0x0114	//  Self Command Register
#define PP_BusCTL					0x0116	//  ISA bus control Register
#define PP_TestCTL					0x0118	//  Test Register
#define PP_AutoNegCTL				0x011C	//  Auto Negotiation Ctrl

#define PP_ISQ						0x0120	//  Interrupt Status
#define PP_RxEvent					0x0124	//  Rx Event Register
#define PP_TxEvent					0x0128	//  Tx Event Register
#define PP_BufEvent					0x012C	//  Bus Event Register
#define PP_RxMiss					0x0130	//  Receive Miss Count
#define PP_TxCol					0x0132	//  Transmit Collision Count
#define PP_LineST					0x0134	//  Line State Register
#define PP_SelfST					0x0136	//  Self State register
#define PP_BusST					0x0138	//  Bus Status
#define PP_TDR						0x013C	//  Time Domain Reflectometry
#define PP_AutoNegST				0x013E	//  Auto Neg Status
#define PP_TxCommand				0x0144	//  Tx Command
#define PP_TxLength					0x0146	//  Tx Length
#define PP_LAF						0x0150	//  Hash Table
#define PP_IA						0x0158	//  Physical Address Register

#define PP_RxStatus					0x0400	//  Receive start of frame
#define PP_RxLength					0x0402	//  Receive Length of frame
#define PP_RxFrame					0x0404	//  Receive frame pointer
#define PP_TxFrame					0x0A00	//  Transmit frame pointer

//  Primary I/O Base Address. If no I/O base is supplied by the user, then this
//  can be used as the default I/O base to access the PacketPage Area.
#define DEFAULTIOBASE				0x0300
#define FIRST_IO					0x020C	//  First I/O port to check
#define LAST_IO						0x037C	//  Last I/O port to check (+10h)
#define ADD_MASK					0x3000	//  Mask it use of the ADD_PORT register
#define ADD_SIG						0x3000	//  Expected ID signature

// On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON.
#ifdef CONFIG_MAC
#define LCSLOTBASE					0xfee00000
#define MMIOBASE					0x40000
#endif

#define CHIP_EISA_ID_SIG			0x630E	//  Product ID Code for Crystal Chip (CS8900 spec 4.3)

// Interrupt Number.
#define INTRQ0						0x0000
#define INTRQ1						0x0001
#define INTRQ2						0x0002
#define INTRQ3						0x0003
#define INTRQ_HIGH_IMPEDENCE		0x0004


// DMA Channel Number.
#define DMRQ0						0x0000
#define DMRQ1						0x0001
#define DMRQ2						0x0002
#define DMRQ_HIGH_IMPEDENCE			0x0003



#ifdef IBMEIPKT
#define EISA_ID_SIG					0x4D24	//  IBM
#define PART_NO_SIG					0x1010	//  IBM
#define MONGOOSE_BIT				0x0000	//  IBM
#else
#define EISA_ID_SIG					0x630E	//  PnP Vendor ID (same as chip id for Crystal board)
#define PART_NO_SIG					0x4000	//  ID code CS8920 board (PnP Vendor Product code)
#define MONGOOSE_BIT				0x2000	//  PART_NO_SIG + MONGOOSE_BUT => ID of mongoose
#endif

#define PRODUCT_ID_ADD				0x0002	//  Address of product ID

// Mask to find out the types of  registers.
#define REG_TYPE_MASK				0x001F

// Eeprom Commands.
#define ERSE_WR_ENBL				0x00F0
#define ERSE_WR_DISABLE				0x0000

// Defines Control/Config register quintuplet numbers.
#define RX_BUF_CFG					0x0003
#define RX_CONTROL					0x0005
#define TX_CFG						0x0007
#define TX_COMMAND					0x0009
#define BUF_CFG						0x000B
#define LINE_CONTROL				0x0013
#define SELF_CONTROL				0x0015
#define BUS_CONTROL					0x0017
#define TEST_CONTROL				0x0019

//  Defines Status/Count registers quintuplet numbers.
#define RX_EVENT					0x0004
#define TX_EVENT					0x0008
#define BUF_EVENT					0x000C
#define RX_MISS_COUNT				0x0010
#define TX_COL_COUNT				0x0012
#define LINE_STATUS					0x0014
#define SELF_STATUS					0x0016
#define BUS_STATUS					0x0018
#define TDR							0x001C

// PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write.
#define SKIP_1						0x0040
#define RX_STREAM_ENBL				0x0080
#define RX_OK_ENBL					0x0100
#define RX_DMA_ONLY					0x0200
#define AUTO_RX_DMA					0x0400
#define BUFFER_CRC					0x0800
#define RX_CRC_ERROR_ENBL			0x1000
#define RX_RUNT_ENBL				0x2000
#define RX_EXTRA_DATA_ENBL			0x4000

// PP_RxCTL - Receive Control bit definition - Read/write.
#define RX_IA_HASH_ACCEPT			0x0040
#define RX_PROM_ACCEPT				0x0080
#define RX_OK_ACCEPT				0x0100
#define RX_MULTICAST_ACCEPT			0x0200
#define RX_IA_ACCEPT				0x0400
#define RX_BROADCAST_ACCEPT			0x0800
#define RX_BAD_CRC_ACCEPT			0x1000
#define RX_RUNT_ACCEPT				0x2000
#define RX_EXTRA_DATA_ACCEPT		0x4000
#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
//  Default receive mode - individually addressed, broadcast, and error free.
#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)

// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write.
#define TX_LOST_CRS_ENBL			0x0040
#define TX_SQE_ERROR_ENBL			0x0080
#define TX_OK_ENBL					0x0100
#define TX_LATE_COL_ENBL			0x0200
#define TX_JBR_ENBL					0x0400
#define TX_ANY_COL_ENBL				0x0800
#define TX_16_COL_ENBL				0x8000

// PP_TxCMD - Transmit Command bit definition - Read-only.
#define TX_START_4_BYTES			0x0000
#define TX_START_64_BYTES			0x0040
#define TX_START_128_BYTES			0x0080
#define TX_START_ALL_BYTES			0x00C0
#define TX_FORCE					0x0100
#define TX_ONE_COL					0x0200
#define TX_TWO_PART_DEFF_DISABLE	0x0400
#define TX_NO_CRC					0x1000
#define TX_RUNT						0x2000

// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write.
#define GENERATE_SW_INTERRUPT		0x0040
#define RX_DMA_ENBL					0x0080
#define READY_FOR_TX_ENBL			0x0100
#define TX_UNDERRUN_ENBL			0x0200
#define RX_MISS_ENBL				0x0400
#define RX_128_BYTE_ENBL			0x0800
#define TX_COL_COUNT_OVRFLOW_ENBL	0x1000
#define RX_MISS_COUNT_OVRFLOW_ENBL	0x2000
#define RX_DEST_MATCH_ENBL			0x8000

// PP_LineCTL - Line Control bit definition - Read/write.
#define SERIAL_RX_ON				0x0040
#define SERIAL_TX_ON				0x0080
#define AUI_ONLY					0x0100
#define AUTO_AUI_10BASET			0x0200
#define MODIFIED_BACKOFF			0x0800
#define NO_AUTO_POLARITY			0x1000
#define TWO_PART_DEFDIS				0x2000
#define LOW_RX_SQUELCH				0x4000

// PP_SelfCTL - Software Self Control bit definition - Read/write.
#define POWER_ON_RESET				0x0040
#define SW_STOP						0x0100
#define SLEEP_ON					0x0200