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📄 hyper104s.s

📁 这是一个uC/OS-II For cs8900的移植项目源代码.可以在uCOSV252.exe上运行
💻 S
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#define  PERIOD_VALUE_1MS	3686

#define  PERIOD_VALUE_10MS	36864
#define  PERIOD_VALUE_100MS	368640

#define  PERIOD_VALUE_1000MS	3686400



// Memory partion

#define  DRAM_BASE_ADDR		0xC0000000

#define  DRAM_SIZE		0x02000000


#define  FIQSTACKEND		DRAM_BASE_ADDR+DRAM_SIZE-4

#define  SVCSTACKEND		FIQSTACKEND-0x00010000

#define  IRQSTACKEND		SVCSTACKEND-0x00010000



// Position of serial port.

#define  COM1UART_SERIAL_OFFSET	0x00010000

#define  COM3UART_SERIAL_OFFSET	0x00050000

#define  SERIAL_SPEED		0x00000001

////////////////////////////////////////

	

	.text



	.globl _start

_start:

	b	ResetHandler 

	b	UndefHandler

	b	SWIHandler

	b	PAbortHandler

	b	DAbortHandler

	b	UnusedHandler

	b	IRQHandler

	b	FIQHandler




////////////////
UndefHandler:

	movs    pc, lr




//UndefHandelr:
//	movs    pc, lr



SWIHandler:

	movs    pc, lr


PAbortHandler:

	subs    pc, lr, #4



DAbortHandler:

	subs    pc, lr, #8



UnusedHandler:

	movs    pc, lr



FIQHandler:

	subs	pc, lr, #4


.globl	OSCtxSw

OSCtxSw:	

	stmfd	sp!,{lr}			// push resume address

	stmfd	sp!,{r0 - r12, lr}		// push rest context

	mrs	r0,SPSR

//	bic	r0, r0, #0x40			// F bit Clear

	bic	r0, r0, #0x80			// F bit Clear


	stmfd	sp!,{r0}			// push CPSR



	ldr	r0,=OSTCBCur			// r0 <= &OSTCBCur

	ldr	r0,[r0]				// r0 <=  OSTCBCur

	str	sp,[r0]				// OSTCBCur->OSTCBStkPtr = sp



	bl	OSTaskSwHook			// Call user defined task switch hook



	ldr	r0,=OSTCBCur			// r0 <= &OSTCBCur

	ldr	r1,=OSTCBHighRdy		// r1 <= &OSTCBHighRdy

	

	ldr	r2,[r1]				// r2 <=  OSTCBHighRdy

	str	r2,[r0]				// OSTCBCur = OSTCBHighRdy



	ldr	r0,=OSPrioCur			// r0 <= &OSPrioCur

	ldr	r1,=OSPrioHighRdy		// r1 <= &OSPrioHighRdy

	

	ldrb	r3,[r1]				// r3 <=  OSPrioHighRdy

	strb	r3,[r0]				// OSPrioCur = OSPrioHighRdy



	ldr	sp,[r2]				// sp <=  OSTCBHighRdy->OSTCBStkPtr

	ldmfd	sp!,{r0}			// restore SP...

	
	msr	SPSR,r0


	ldmfd   sp!,{r0 - r12, lr,pc}		// Load task's context & SPSR-> CPSR & Run task




IRQHandler:

	mrs	r8, spsr


	ldr	r12,=0x90050000
	ldr	r11,[r12, #0x00]

	ldr	r10, =0x04000000

	tst	r10, r11
	bne	OSTimer0IRQ

	msr	spsr, r8

	subs    pc,lr,#4


OSTimer0IRQ:


	ldr	r12, =0x90000000

	//OSTimer Interrupt Source Bit Clear

	mov	r11, #0x01

	str	r11, [r12, #0x14]

	ldr	r11, [r12, #0x10]

	ldr	r10, =PERIOD_VALUE_10MS

	add	r10, r10, r11

	str	r10, [r12, #0x00]

	stmfd	sp!, {r0-r3}

	mov	r2,sp			// copy FIQ's sp -> r2

	add	sp,sp,#16		// recover FIQ's sp 

	sub	r3,lr,#4		// copy return address -> r3

	mov	r1, r8			// copy SPSR -> r1 (SPSR=r8)

//	orr	r1, r1, #0x40		// F bit Setting

	orr	r1, r1, #0x80		// I bit Setting

	msr	SPSR, r1		// update SPSR

	ldr	r0,=OSTickISR		

	movs	pc,r0			// Mode Change from FIQ mode to SVC mode


////////////////////////////
OSTickISR:

	stmfd	sp!,{r3}		// push SVC's pc

	stmfd	sp!,{r4-r12,lr}		// push SVC's r14, r12-r4

	mov	r4,r2			// copy FIQ's sp -> r4

	ldmfd	r4!,{r0-r3}		// pop SVC's r3-r0

	stmfd	sp!,{r0-r3}		// push SVC's r3-r0

	mrs	r5,CPSR			// copy CPSR -> r5

//	bic	r5, r5, #0x40		// F bit clear

	bic	r5, r5, #0x80		// I bit clear

	stmfd	sp!,{r5}		// push SVC's CPSR



	ldr	r0,=OSIntNesting	// Notify uC/OS-II of ISR


	ldrb	r1,[r0]

	ADD	r1,r1,#1

	strb	r1,[r0]

	

	bl	OSTimeTick		// Process system tick

    	bl	OSIntExit		// Notify uC/OS-II of end of ISR



	ldmfd	sp!,{r0}

	msr	SPSR,r0


	ldmfd   sp!,{r0 - r12, lr , pc}^      




.extern OSTCBCur
.extern OSTaskSwHook
.extern OSTCBHighRdy
.extern OSPrioCur
.extern OSPrioHighRdy

.globl OSIntCtxSw

OSIntCtxSw:
	add	sp,sp,#16
	ldr 	r0,=OSTCBCur
	ldr	r0,[r0]
	str	sp,[r0]
	bl	OSTaskSwHook
	ldr	r0,=OSTCBCur
	ldr	r1,=OSTCBHighRdy
	ldr	r2,[r1]
	str	r2,[r0]
	ldr	r0,=OSPrioCur
	ldr	r1,=OSPrioHighRdy
	ldrb	r3,[r1]
	strb	r3,[r0]
	ldr	sp,[r2]
	ldmfd	sp!,{r0}
	msr	spsr,r0
	ldmfd	sp!,{r0 - r12,lr,pc}^



ResetHandler:



	// First, mask ALL interrupts.

	ldr	r1, =0x90050000

	mov	r2, #0x00

	str	r2, [r1, #0x04]	// ICMR.



	

	// Switch the CPU to 206 MHz by writing the PPCR.

	// This change PLL of clock.

	// view sa1110 manual 9.5.7.3. and value is page 8-2.

	mov	r1, #0x90000000

	add	r1, r1, #0x20000

	mov 	r2, #0x0b
	str	r2, [r1, #0x04]		// PPCR.



	mov	r1, #0xA0000000		// MDCNFG base address



	ldr	r2, =0x55555557

	str	r2, [r1, #0x04]		// MDCAS00

	str	r2, [r1, #0x20]		// MDCAS20



	ldr	r2, =0x55555555

	str	r2, [r1, #0x08]		// MDCAS01

	str	r2, [r1, #0x24]		// MDCAS21



	ldr	r2, =0x55555555

	str	r2, [r1, #0x0C]		// MDCAS02

	str	r2, [r1, #0x28]		// MDCAS22



	ldr	r2, =0x003000C1		// MDREFR

	str	r2, [r1, #0x1C]



	ldr	r2, =0x0007154		// MDCNFG

	str	r2, [r1, #0x00]



	// Issue read requests to disabled bank to start refresh.

	ldr	r1, =0xC0000000


.rept	8
	ldr 	r0,[r1]
.endr	
	mov 	r1, #0xA0000000
	
	ldr	r2, =0x72547255
	str	r2,[r1, #0x00]

// Set Static Memory.

// use MSC0, MSC1, MSC2, SMCNFG.

// Set Static Memory.


	// Set up Static space.

	mov	r1, #0xA0000000

	ldr	r2, =0x4b944b94		

	str	r2, [r1, #0x10]		// MSC0 (CS0, CS1).



	mov	r1, #0xA0000000

	ldr	r2, =0x00004b94

	str	r2, [r1, #0x14]		// MSC1 (CS2, CS3).



	ldr	r2, =0x00000000

	str	r2, [r1, #0x2C]		// MSC2 (CS4, CS5).



	ldr	r2, =0xafccefcc

	str	r2, [r1, #0x30]		// SMCNFG.



	// Set up PCMCIA space.

	ldr	r2, =0x994a994a

	str	r2, [r1, #0x18]		// MECR.

	mov	r3, #0x12000000
	mov 	r2, #0x5000
	str	r2, [r3]
	mov 	r4, #0x20000



	ldr	r2, =0x90000000

	mov	r1, #0x00

	str	r1, [r2, #0x10]

	ldr	r1, =36864      //PERIOD_VALUE_10MS

	str	r1, [r2, #0x00]

	mov	r1, #0x01

	str	r1, [r2, #0x1C]

	mov	r1, #0x00

	str	r1, [r2, #0x18]

	

	//OSTimer Interrupt Source Bit Clear

	mov	r1, #0x01

	str	r1, [r2, #0x14]

	mov	r1, #0x02

	str	r1, [r2, #0x14]

	mov	r1, #0x04

	str	r1, [r2, #0x14]

	mov	r1, #0x08

	str	r1, [r2, #0x14]


// Serial port initiallize.

// use UTCR0,1,2,3, UTDR, UTSR0,1.



	// Serial port 3.

	mov	r1, #0x80000000

	add	r1, r1, #COM3UART_SERIAL_OFFSET

	mov	r2, #0xFF

	str	r2, [r1, #0x1C]		// UTSR0.

	

	// Set the serial port to sensible defaults:

	//	no break, no interrupts, no parity, 8 databits, 1 stopbit.

	mov	r2, #0x00

	str	r2, [r1, #0x0C]		// UTCR3.

	mov	r2, #0x08

	str	r2, [r1, #0x00]		// UTCR0.



	// Set Baudrate.

	// view sa1110 manual 11.11.4.1.

	mov	r2, #0x00

	str	r2, [r1, #0x04]		// UTCR1.

	mov	r2, #SERIAL_SPEED	// baudrate.

	str	r2, [r1, #0x08]		// UTCR2.

	

	// Enable the transmitter.

	//mov	r1, #0x80000000

	//add	r1, r1, #COM3UART_SERIAL_OFFSET

	mov	r2, #0x02		// UTCR3 tx.

	str	r2, [r1, #0x0C]		// UTCR3.




	// Fiq and Irq Interrupt Disable

	ldr     r0, =0x000000d1		// FIQ Mode sp Setting

	msr     cpsr, r0

	ldr     r13, =FIQSTACKEND


	// Fiq and Irq Interrupt Diable

	ldr     r0, =0x000000d2		// IRQ Mode sp Setting

	msr     cpsr, r0

	ldr     r13, =IRQSTACKEND

	

	

	// Fiq Interrupt Enable

	ldr     r0, =0x000000d3		// SVC Mode sp Setting

	msr     cpsr, r0

	ldr     r13, =SVCSTACKEND


.extern BeforeMain

jump_to_c:

	b	BeforeMain



.global	OSTimer0_Period_Setting	

OSTimer0_Period_Setting:

	stmfd	sp!, {r1-r2,lr}

	ldr	r2, =0x90000000

	mov	r1, #0x00

	str	r1, [r2, #0x10]

	ldr	r1, =PERIOD_VALUE_10MS

	str	r1, [r2, #0x00]

	mov	r1, #0x01

	str	r1, [r2, #0x1C]

	mov	r1, #0x00

	str	r1, [r2, #0x18]

	

	//OSTimer Interrupt Source Bit Clear

	mov	r1, #0x01

	str	r1, [r2, #0x14]

	mov	r1, #0x02

	str	r1, [r2, #0x14]

	mov	r1, #0x04

	str	r1, [r2, #0x14]

	mov	r1, #0x08

	str	r1, [r2, #0x14]



	ldmfd	sp!, {r1-r2,pc}



.globl OSTimer0_Interrupt_Setting

OSTimer0_Interrupt_Setting:

	stmfd	sp!, {r1-r2, lr}


	ldr	r2, =0x90050000



	mov	r1, #0x00

	str	r1, [r2, #0x0C]

	

	//OS Timer Interrupt is set IRQ
	ldr	r1, =0x00 //ssenja //irq
	

	str	r1, [r2, #0x08] //ICLR

	//OS Timer Interrupt Mask Register Set

	ldr	r1, =0x04000000


	str	r1, [r2, #0x04] //ICMR
	ldmfd	sp!, {r1-r2, pc}



.globl 	OST0_Interrupt_Mask_Disable

.globl 	OST0_Interrupt_Mask_Enable


OST0_Interrupt_Mask_Disable:

	stmfd	sp!, {r0-r2,lr}

	ldr	r2, =0x90050000

	//OS Timer Interrupt Mask Register is Clear

	ldr	r0, =0x04000000

	ldr	r1, [r2, #0x04] //ICMR
	bic	r1, r1, r0

	str	r1, [r2, #0x04] //ICMR


	ldmfd	sp!, {r0-r2,pc}

	

OST0_Interrupt_Mask_Enable:


	stmfd	sp!, {r0-r2,lr}

	ldr	r2, =0x90050000

	

	//OS Timer Interrupt Mask Register is Set

	ldr	r0, =0x04000000

	ldr	r1, [r2,#0x04] //ICMR
	orr	r1, r1, r0

	str	r1, [r2,#0x04] //ICMR


	ldmfd	sp!, {r0-r2,pc}




.extern	OSTaskSwHook

.extern	OSRunning

.extern	OSTCBHighRdy

.extern	OSStartHighRdy

.globl OSStartHighRdy

OSStartHighRdy:



	bl	OSTaskSwHook			// Call user defined task switch hook



	ldr	r0,=OSRunning			// Indicate that multitasking has started

	mov	r1,#1

	strb	r1,[r0]



	ldr	r0,=OSTCBHighRdy		// r0 <= &OSTCBHighRdy

	ldr	r0,[r0]				// r0 <=  OSTCBHighRdy



	ldr	sp,[r0]				// sp <=  OSTCBHighRdy->OSTCBStkPtr



	ldmfd	sp!,{r0}			// restore SP...

	msr	CPSR,r0			// CPSR <- R0

	ldmfd   sp!,{r0 - r12, lr , pc}		// Load task's context & Run task

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