📄 c5410_clk.cdb
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_stackString, _stackSeg, _midPlace"} else {"9\0, _argsString, _argsSeg, _midPlace, \ _sysdataString, _sysdataSeg, _thirdPlace, \ _trcinitString, _trcinitSeg, _midPlace, \ _gblinitString, _gblinitSeg, _midPlace, \ _memObjString, _memObjSeg, _midPlace, \ _sysregsString, _regsSeg, _midPlace, \ _biosString, _biosSeg, _midPlace, \ _biosNORPTBString, _biosNORPTBSeg, _midPlace, \ _stackString, _stackSeg, _midPlace"}}}} else {if (self.REUSE == 0 && self.USERCMD == 0) {"19\0, _argsString, _argsSeg, _midPlace, \ _sysdataString, _sysdataSeg, _thirdPlace, \ _trcinitString, _trcinitSeg, _midPlace, \ _gblinitString, _gblinitSeg, _midPlace, \ _memObjString, _memObjSeg, _midPlace, \ _sysinitString, _initSeg, _sysinitPlace, \ _sysregsString, _regsSeg, _midPlace, \ _bssString, _bssSeg, _firstPlace, \ _farString, _farSeg, _secondPlace, \ _cinitString, _cinitSeg, _midPlace, \ _pinitString, _pinitSeg, _midPlace, \ _dataString, _dataSeg, _midPlace, \ _constString, _constSeg, _midPlace, \ _switchString, _switchSeg, _midPlace, \ _cioString, _cioSeg, _midPlace, \ _textString, _textSeg, _midPlace, \ _frtString, _frtSeg, _midPlace, \ _biosString, _biosSeg, _midPlace, \ _stackString, _stackSeg, _midPlace"} else {if (self.REUSE == 0 && self.USERCMD == 1) {"9\0, _argsString, _argsSeg, _midPlace, \ _sysdataString, _sysdataSeg, _thirdPlace, \ _trcinitString, _trcinitSeg, _midPlace, \ _gblinitString, _gblinitSeg, _midPlace, \ _memObjString, _memObjSeg, _midPlace, \ _sysinitString, _initSeg, _sysinitPlace, \ _sysregsString, _regsSeg, _midPlace, \ _biosString, _biosSeg, _midPlace, \ _stackString, _stackSeg, _midPlace"} else {if (self.REUSE == 1 && self.USERCMD == 0) {"18\0, _argsString, _argsSeg, _midPlace, \ _sysdataString, _sysdataSeg, _thirdPlace, \ _trcinitString, _trcinitSeg, _midPlace, \ _gblinitString, _gblinitSeg, _midPlace, \ _memObjString, _memObjSeg, _midPlace, \ _sysregsString, _regsSeg, _midPlace, \ _bssString, _bssSeg, _firstPlace, \ _farString, _farSeg, _secondPlace, \ _cinitString, _cinitSeg, _midPlace, \ _pinitString, _pinitSeg, _midPlace, \ _dataString, _dataSeg, _midPlace, \ _constString, _constSeg, _midPlace, \ _switchString, _switchSeg, _midPlace, \ _cioString, _cioSeg, _midPlace, \ _textString, _textSeg, _midPlace, \ _frtString, _frtSeg, _midPlace, \ _biosString, _biosSeg, _midPlace, \ _stackString, _stackSeg, _midPlace"} else {"8\0, _argsString, _argsSeg, _midPlace, \ _sysdataString, _sysdataSeg, _thirdPlace, \ _trcinitString, _trcinitSeg, _midPlace, \ _gblinitString, _gblinitSeg, _midPlace, \ _memObjString, _memObjSeg, _midPlace, \ _sysregsString, _regsSeg, _midPlace, \ _biosString, _biosSeg, _midPlace, \ _stackString, _stackSeg, _midPlace"}}}}) prop _firstPlace :: 0 prop _secondPlace :: 0 + 1 prop _thirdPlace :: 0 + 2 prop _midPlace :: (0x7ffff / 2) prop _sysinitPlace :: (0x7ffff / 2) prop _argsString :: ("%8t .args: fill=0 {%12t\n *(.args)\n . += 0x%1x;%8t\n }\0, _argsSize") prop _bssString :: ("%8t .bss: {}") prop _farString :: ("%8t .far: {}") prop _cinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.CINITSEG == MEM.LOADCINITSEG) {"%8t .cinit: {}"} else {"%8t .cinit: {} load > %1s, run\0, _loadcinitSeg"}} else {"%8t .cinit: {}"}) prop _pinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.PINITSEG == MEM.LOADPINITSEG) {"%8t .pinit: {}"} else {"%8t .pinit: {} load > %1s, run\0, _loadpinitSeg"}} else {"%8t .pinit: {}"}) prop _trcinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.TRCINITSEG == MEM.LOADTRCINITSEG) {"%8t .trcdata: {}"} else {"%8t .trcdata: {} load > %1s, run\0, _loadtrcinitSeg"}} else {"%8t .trcdata: {}"}) prop _gblinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.BIOSINITSEG == MEM.LOADBIOSINITSEG) {"%8t .gblinit: {}"} else {"%8t .gblinit: {} load > %1s, run\0, _loadgblinitSeg"}} else {"%8t .gblinit: {}"}) prop _dataString :: ("%8t .data: {}") prop _constString :: (if (self.ENABLELOADSEG == 1) {if (MEM.CONSTSEG == MEM.LOADCONSTSEG) {"%8t .const: {}"} else {"%8t .const: {} load > %1s, run\0, _loadconstSeg"}} else {"%8t .const: {}"}) prop _switchString :: (if (self.ENABLELOADSEG == 1) {if (MEM.SWITCHSEG == MEM.LOADSWITCHSEG) {"%8t .switch: {}"} else {"%8t .switch: {} load > %1s, run\0, _loadswitchSeg"}} else {"%8t .switch: {}"}) prop _sysmemString :: ("%8t .sysmem: {}") prop _cioString :: ("%8t .cio: {}") prop _memObjString :: ("%8t .mem: {}") prop _sysdataString :: (if ((GBL.ROM == 0) && (GBL.DSPTYPE == 54)) {"%8t .sysdata: align = 128 {%12t\n GBL_A_SYSPAGE = .;\n GBL_A_SYSDP = GBL_A_SYSPAGE >> 7;\n %8t }"} else {"%8t .sysdata: {}"}) prop _sysinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.INITSEG == MEM.LOADINITSEG) {"%8t .sysinit: {}"} else {"%8t .sysinit: {} load > %1s, run\0, _loadinitSeg"}} else {"%8t .sysinit: {}"}) prop _sysregsString :: ("%8t .sysregs: {}") prop _textString :: (if (self.ENABLELOADSEG == 1) {if (MEM.TEXTSEG == MEM.LOADTEXTSEG) {"%8t .text: {}"} else {"%8t .text: {} load > %1s, run\0, _loadtextSeg"}} else {"%8t .text: {}"}) prop _frtString :: ("%8t frt: {}") prop _biosString :: (if (self.ENABLELOADSEG == 1) {if (MEM.BIOSSEG == MEM.LOADBIOSSEG) {"%8t .bios: {}"} else {"%8t .bios: {} load > %1s, run\0, _loadbiosSeg"}} else {"%8t .bios: {}"}) prop _biosNORPTBString :: (if (self.ENABLELOADSEG == 1) {if (MEM.BIOSNORPTBSEG == MEM.LOADBIOSNORPTBSEG) {"%8t .bios:.norptb: {}"} else {"%8t .bios:.norptb: {} load > %1s, run\0, _loadbiosNORPTBSeg"}} else {"%8t .bios:.norptb: {}"}) prop _stackString :: (if (GBL.DSPTYPE == 62) {"%8t .stack: fill=0xc0ffee {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = GBL_stackbeg + 0x%1x - 1;%12t\n _HWI_STKBOTTOM = GBL_stackbeg + 0x%1x - 4 & ~7;%12t\n _HWI_STKTOP = GBL_stackbeg;%8t\n }\0, _stackSize, _stackSize"} else {if (GBL.DSPTYPE == 54) {"%8t .stack: fill=0xbeef {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = ((GBL_stackbeg + 0x%1x - 1) & 0xfffe) ;%8t\n _HWI_STKBOTTOM = GBL_stackend;%12t\n _HWI_STKTOP = GBL_stackbeg;%8t\n }\0, _stackSize"} else {if (GBL.DSPTYPE == 55) {"%8t .stack: fill=0xbeef {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = (GBL_stackbeg + 0x%1x - 1) ;%12t\n _HWI_STKBOTTOM = (GBL_stackend+1);%12t\n _HWI_STKTOP = (GBL_stackbeg);%8t\n }\0, _cmd55stksz"} else {"%8t .stack: fill=0xbeef {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = GBL_stackbeg + 0x%1x - 1;%8t\n }\0, _cmd55stksz"}}}) prop _memHdrSize :: 8 prop GenLinkEpilogue :: ("%0t}") prop _stackSeg :: MEM.STACKSEG prop _textSeg :: MEM.TEXTSEG prop _frtSeg :: MEM.TEXTSEG prop _biosSeg :: MEM.BIOSSEG prop _biosNORPTBSeg :: MEM.BIOSNORPTBSEG prop _dataSeg :: MEM.DATASEG prop _cioSeg :: MEM.CIOSEG prop _sysmemSeg :: MEM.SYSMEMSEG prop _constSeg :: MEM.CONSTSEG prop _initSeg :: MEM.INITSEG prop _pinitSeg :: MEM.PINITSEG prop _trcinitSeg :: MEM.TRCINITSEG prop _gblinitSeg :: MEM.BIOSINITSEG prop _regsSeg :: BIOSREGS prop _sysdataSeg :: MEM.SYSDATASEG prop _argsSeg :: MEM.ARGSSEG prop _argsSize :: MEM.ARGSSIZE prop _bssSeg :: MEM.BSSSEG prop _farSeg :: MEM.FARSEG prop _cinitSeg :: MEM.CINITSEG prop _memObjSeg :: MEM.CFGOBJSEG prop _switchSeg :: MEM.SWITCHSEG prop _loadtextSeg :: MEM.LOADTEXTSEG prop _loadbiosSeg :: MEM.LOADBIOSSEG prop _loadbiosNORPTBSeg :: MEM.LOADBIOSNORPTBSEG prop _loadconstSeg :: MEM.LOADCONSTSEG prop _loadinitSeg :: MEM.LOADINITSEG prop _loadpinitSeg :: MEM.LOADPINITSEG prop _loadtrcinitSeg :: MEM.LOADTRCINITSEG prop _loadgblinitSeg :: MEM.LOADBIOSINITSEG prop _loadcinitSeg :: MEM.LOADCINITSEG prop _loadswitchSeg :: MEM.LOADSWITCHSEG prop AllocInst :: (if (self.iAllocHeap == 1) {"1\0, _instAllocDesc, _objMemSeg, _placement"} ) prop _instAllocDesc :: (if self.INITSEG.iAllocHeap && self.REUSE && self.INITSEG == self {"%8t .%0r$heap: {%12t\n %0r$B = .;\n%12t\n _%0r_base = .;\n . += 0x%2x;\n *(.sysinit)\n %0r$L = . + 0x%3x - %0r$B;\n _%0r_length = . + 0x%3x - %0r$B;\n . += 0x%1x;%8t\n }\0, _heapsize, _sysinitgap, _heaplen"} else {"%8t .%0r$heap: {%12t\n %0r$B = .;\n _%0r_base = .;\n %0r$L = 0x%2x;\n _%0r_length = 0x%2x;\n . += 0x%1x;%8t\n }\0, _heapsize, _heaplen"}) prop _objMemSeg :: self prop _placement :: 0x7ffff - 1 prop _heapsize :: (self.iHeapSize) prop _heaplen :: (self.iHeapSize) prop _sysinitgap :: 2 * 1 prop GenInstLink :: (if GBL.DSPTYPE == 62 {"%0r %16t: origin = 0x%1x, %40tlen = 0x%2x%4t\0, _origin, _len"} else {if GBL.DSPTYPE == 55 {"%0r: %16torigin = 0x%1x, %40tlen = 0x%2x%4t\0, _cmd55origin, _cmd55len"} else {"PAGE %3d: %14t%0r: %26torigin = 0x%1x, %50tlen = 0x%2x%4t\0, _origin, _len, _page"}}) prop localInit :: ($d = "ok", scan ($i; MEM) {if ($i.space == "code" && $i.iAllocHeap == 1) {$d = self.error("Code memory cannot have a heap")} }, if (self.SEGZERO.iAllocHeap == 1) {self.SEGZERO.iReqHeapCount++} else {$d = self.error("Segment for DSP/BIOS objects must be a memory segment with a heap")}, if (self.MALLOCSEG.iAllocHeap == 1) {self.MALLOCSEG.iReqHeapCount++} else {$d = self.error("Segment for malloc()/free() must be a memory segment with a heap")}, $d) prop _page :: (self.page) prop _origin :: (self.base) prop _len :: (self.len) prop maxObjs :: (32767) prop codeMember :: (if GBL.DSPTYPE == 62 {$1.space == "code" || $1.space == "code/data"} else {if GBL.DSPTYPE == 54 {$1.space == "code"} else {$1.space == "code/data"}}) prop dataMember :: (if GBL.DSPTYPE == 62 {($1.space == "data" || $1.space == "code/data") && $1 != MEM_NULL} else {if GBL.DSPTYPE == 54 {(($1.space != "code") && ($1 != MEM_NULL)) && $1.space != "io"} else {(($1.space == "code/data") && ($1 != MEM_NULL))}}) prop dataNullMember :: (if GBL.DSPTYPE == 62 {$1.space == "data" || $1.space == "code/data"} else {if GBL.DSPTYPE == 54 {$1.space != "code" && $1.space != "io"} else {$1.space == "code/data"}}) prop dataCodeMember :: (if GBL.DSPTYPE == 62 {($1.space == "data" || $1.space == "code/data") && $1 != MEM_NULL} else {if GBL.DSPTYPE == 54 {$1.space == "code" && $1 != MEM_NULL} else {$1.space == "code/data" && $1 != MEM_NULL}}) prop memWritable :: (self.iIsModifiable && self.iDelUser != "MEM") prop checkOverlap :: ($f = if $3 == $2 - 1 {$2} else {$3}, $d = "ok", if (self.doCheckOverlap) {scan ($i; MEM) {if ($i != $1 && (GBL.DSPTYPE == 62 || GBL.DSPTYPE == 55 || $i.space == $1.space)) {if (!($i == CACHE_L2 && GBL.L2CONFIGURE == 0)) {$b = $i.base, $e = $i.base + $i.len - 1, if ($f >= $b && $2 <= $e) {$d = self.error("Segment will overlap with another memory segment or cache configuration")} } } }} , $d) prop checkHeapId :: ($e = "ok", scan ($i; MEM) {if ($i.iAllocHeap == 1 && $i.iUserHeapId == 1 && $i.iHeapId == $1 && $i.iHeapId != @segment_name) {$e = self.error("This identifier label is already in use"), break} }, $e) global gUser :: "USER" { prop Visible :: 0 prop Writable :: 0 prop NoGen :: 1 } global gSetOf :: 0 { prop Visible :: 0 prop Writable :: 0 prop NoGen :: 1 } global gNumOf :: 8 { prop Visible :: 0 prop Writable :: 0 prop NoGen :: 1 } global gDirty :: 1 { prop Visible :: 0 prop Writable :: 0 prop NoGen :: 1 } global gInitFlag :: 1 { prop Visible :: 0 prop Writable :: 0 prop NoGen :: 1 } global gInit :: = ($a = 0, $b = 0, scan ($i; self) {if ($i.IsConfObj()) {$a += 1, if (self.isFinite) {$b |= 1 << $i.iId} } }, self.gNumOf = $a, self.gSetOf = $b, if (self.gInitFlag == 0) {self.localInit()} , self.gInitFlag = 1) { prop Visible :: 0 prop Writable :: 0 prop NoGen :: 1 } global gNumHeap :: = ($a = 0, scan ($i; MEM) {if ($i != MEM_NULL) {$a += $i.iAllocHeap} }, $a) { prop NoGen :: 0 } global REUSE :: = (if self.INITSEG.space != "code" && self.INITSEG.iAllocHeap == 1 {self.SAVEREUSE} else {0}) { prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}" prop Label :: "Reuse Startup Code Space" prop JSName :: "REUSECODESPACE" prop Visible :: 1 prop Writable :: self.INITSEG.space != "code" && self.INITSEG.iAllocHeap == 1 prop NoGen :: 1 prop Set :: (self.SAVEREUSE = $1, "ok") } global SAVEREUSE :: 0 { prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}" prop NoGen :: 1 } global doCheckOverlap :: 1 { prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}" prop Visible :: 0 prop Writable :: 1 prop NoGen :: 1 } global MAPSELECT :: "Map 1" { prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}" prop Label :: "Map Mode" prop JSName :: "MAPMODE" prop Enum :: "Map 0,Map 1" prop Visible :: GBL.DSPTYPE == 62 prop Writable :: 0 && GBL.DSPSUBTYPE != 6211 && GBL.DSPSUBTYPE != 6711 prop NoGen :: 1 prop Set :: (if ($1 != self.MAPSELECT) {if ($1 == "Map 0") {scan ($i; MEM) {if ($i.base >= 0x00000000 && $i.base <= 0x003fffff) {$i.base = $i.base + 0x01400000 - 0x00000000} else {if ($i.base >= 0x00400000 && $i.base <= 0x017fffff) {$i.base = $i.base + 0x00000000 - 0x00400000} }}} , if ($1 == "Map 1") {scan ($i; MEM) {if ($i.base >= 0x01400000 && $i.base <= 0x017fffff) {$i.base = $i.base + 0x00000000 - 0x01400000} else {if ($i.base >= 0x00000000 && $i.base <= 0x013fffff) {$i.base = $i.base + 0x00400000 - 0x00000000} }}} , if ($1 != "Map 0" && $1 != "Map 1") {self.error("Invalid memory map selection")} } , self.MAPSELECT = $1, "ok") } global ARGSSIZE :: 4 { prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}" prop Format :: "0x%04x" prop Style :: 0x01 | 0x02 prop Label :: "Argument Buffer Size" prop JSName :: "ARGSSIZE" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop Set :: (if ($1 < 4) {self.error("The 'arguments' section must have at least 4 words.")} else {self.ARGSSIZE = $1, "ok"}) } global ARGSSEG :: IDATA { prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}" prop MemberType :: MEM prop MemberTest :: self.dataMember($1) prop Label :: "Argument Buffer Section (.args)" prop JSName :: "ARGSSEG" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop TabName :: "BIOS Data" } global BIOSSEG :: IPROG { prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}" prop MemberType :: MEM prop MemberTest :: self.codeMember($1) prop Label :: "BIOS Code Section (.bios)" prop JSName :: "BIOSSEG" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop TabName :: "BIOS Code" } global STACKSIZE :: 256 { prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}" prop Format :: "0x%04x" prop Style :: 0x01 | 0x02 prop Label :: "Stack Size (MAUs)" prop JSName :: "STACKSIZE" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop Set :: (if ($1 < GlobalStatus.MinStackSize) {self.error("The software stack must be at least as large as the Estimated Minimum Stack Size.")} else {self.STACKSIZE = $1, "ok"}) } global USERCMD :: 0 { prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}" prop Label :: "User .cmd File For Non-DSP/BIOS Sections" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop TabName :: "Compiler Sections" } global STACKSEG :: IDATA { prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}" prop MemberType :: MEM prop MemberTest :: self.dataMember($1) prop Label :: "Stack Section (.stack)" prop JSName :: "STACKSEG" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop TabName :: "BIOS Data" prop Set :: (if (GBL.DSPTYPE == 55) {(MEM.STACKSEG = $1), (MEM.SYSSTACKSEG = $1)} else {(MEM.STACKSEG = $1)}, "ok") } global ENABLELOADSEG :: 0 { prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}" prop Label :: "Specify Separate Load Addresses" prop JSName :: "ENABLELOADADDR" prop Visible :: 1 prop Writable :: 1 prop NoGen :: 1 prop TabName :: "Load Address" } global LOADBIOSSEG :: IPROG { prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}" prop MemberType :: MEM prop MemberTest :: self.codeMember($1) prop Label :: "Load Address - BIOS Code Section (.bios)" prop JSName :: "LOADBIOSSEG" prop Visible :: 1 prop Writable :: (self.ENABLELOADSEG == 1) prop NoGen :: 1 prop TabName :: "Load Address" } global BIOSNORPTBSEG :: IPROG { prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}" prop MemberType :: MEM prop MemberTest :: (self.codeMember($1) && (($1.base + $1.len) <= 0x8000)) prop Label :: "BIOS NORPTB Section (.bios:.norptb)" prop JSName :: "BIOSNORPTBSEG" prop Visible :: (GBL.FARMODE == 1) prop Writable :: (GBL.FARMODE == 1) prop NoGen :: 1 prop TabName :: "BIOS Code" } global LOADBIOSNORPTBSEG :: IPROG { prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}" prop MemberType :: MEM
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