spi_dma.txt

SPI_DMA开发程序例程,介绍DMA数据传输

.title "SPI_DMA_BIOS.asm"
    
	.global _SPI_DMA_Init

	.mmregs
	
;McBSP REGISTERS
DRR20	.SET	20H
DRR10	.SET	21H
DXR20	.SET	22H
DXR10	.SET	23H
SPSA0	.SET	38H
SPSD0	.SET	39H

;McBSP SUB-REGISTERS, USE SPSAx FOR INDEXING
SPCR10	.SET	00H
SPCR20	.SET	01H
RCR10	.SET	02H
RCR20	.SET	03H
XCR10	.SET	04H
XCR20	.SET	05H
SRGR10	.SET	06H
SRGR20	.SET	07H
MCR10	.SET	08H
MCR20	.SET	09H
RCERA0	.SET	0AH
RCERB0	.SET	0BH
XCERA0	.SET	0CH
XCERB0	.SET	0DH
PCR0	.SET	0EH

;DMA REGISTERS
DMPREC  .SET    54H
DMSA    .SET    55H
DMSDI   .SET    56H
DMSDN   .SET    57H

;DMA SUB-REGISTERS, USE DMSAx FOR INDEXING
DMSRC1  .SET    05H
DMDST1  .SET    06H
DMCTR1  .SET    07H
DMSFC1  .SET    08H
DMMCR1  .SET    09H
DMIDX0  .SET    20H

	
		.sect "SPI_DMA"
	
***********************************************************
;Phototype: void SPI_DMA_INIT(void);
***********************************************************
		
_SPI_DMA_Init:
		    PSHD	ST0
		    PSHD	ST1
		    RSBX	CPL	                      ;set CPL=0 to select DP BASE addressing
		    NOP
		    NOP
		    NOP
		    LD		#0, DP
		                                                                                    
			stm	SPCR10, SPSA0          		  ;write subaddress of McBSP0
			stm #0000H, SPSD0                 ;reset Rrst			
			stm	SPCR20, SPSA0                 ;write subaddress of McBSP0
			stm #0000H, SPSD0                 ;reset Xrst,Frst,Grst
			RPT #100
			NOP
			
			stm SPCR10, SPSA0
			stm #0001000010000000b, SPSD0
			;    ---10-----------:             clk STOP MODE WITHOUT DELAY
			;    --------1-------:             dx ENABLED
			;    ----------00----:             rint DRIVED BY rddy
			stm SPCR20, SPSA0
			stm #0000001100110000b, SPSD0
			;    ------11--------:             free MODE ENABLED,soft MODE DISABLED
                        ;    ----------11----:             xint DRIVED BY xrdy
                        stm PCR0, SPSA0			           ;write subaddress of McBSP0
			stm #0000111100001101b,SPSD0      
			;	-----1-----------: FSXM
			;	------1----------: FSRM
			;	-------1---------: CLKXM
			;	--------1--------: CLKRM
			;	-------------1---: FSXP
			;	--------------1--: FSRP
			;	---------------0-: CLKXP
			;	----------------1: CLKRP
			stm SRGR20,SPSA0
			stm #0011000000010001b,SPSD0
			;	---1-------------: CLKSM
			;	----1------------: FSGM
			;	-----000000010111: FPER :16+1=17 CLKS
			stm SRGR10,SPSA0
			stm #0001111101000000b,SPSD0
			;	 00000000--------: FWID :15+1=16 CLKS
			;	---------00000100: CLKGDV
			stm XCR20,SPSA0
			stm #0000000001000000b,SPSD0         ;XCR2[1-0]=01,XDATDLY
			stm RCR20,SPSA0
			stm #0000000001000000b,SPSD0         ;RCR2[1-0]=01,RDATDLY

			stm RCR10,SPSA0
			stm #0000000001000000b,SPSD0
			;	 -0000000--------: RFRLEN1=0, 1 WORD PER FRAME
			;	 --------010-----: RWDLEN1=010, 16 BIT PER WORD
			stm XCR10,SPSA0
			stm #0000000001000000b,SPSD0
			;	---------010-----: XWDLEN1
			;	--0000001--------: XFRLEN1
			
			nop
			nop
			
			stm #0000000010011110b,DXR10
		    ;    00000000--------: invalid 8 bit
		    ;    --------1-------: start bit
		    ;    ---------001----: select CH0
		    ;    ------------1---: select unipolar
		    ;    -------------1--: select single ended
		    ;    --------------10: select internal clock mode
		    
		    
		    stm DMSRC1,DMSA
		    stm DRR10,DMSDN                ;set source address to DRR10
		    stm DMDST1,DMSA       
		    stm #3000H,DMSDN               ;set destination address to 3000
		    stm DMCTR1,DMSA
		    stm #100H,DMSDN   ;set buffer size to 100 
		    stm DMSFC1,DMSA
		    stm #0001000000000000b,DMSDN
		    ;    0001------------:(DSYN) McBSP0 receive sync event
		    ;    ----0-----------:(DBLW) Single-word mode 
		    ;    -----000--------:       Reserved
		    ;    --------00000000:(Frame Count) Frame count  is not relevant in ABU mode
		    stm DMMCR1,DMSA
		    stm #0101000001001101b,DMSDN
		    ;    0---------------:(AUTOINIT) Auto-initialization disable
		    ;    -1--------------:(DINM)     DMA Interrupts enabled
		    ;    --0-------------:(IMOD)     Interrupt at full buffer
		    ;    ---1------------:(CTMOD)    ABU(non-decrement)mode
		    ;    ----0-----------:           Reserved
		    ;    -----000--------:(SIND)     No modify on source address(DRR0)
		    ;    --------01------:(DMS)      Source in data space
		    ;    ----------0-----:           Reserved 
		    ;    -----------011--:(DIND)     Post increment destination address with DMIDX0
		    ;    --------------01:(DMD)      Destination in data space
		    stm DMIDX0,DMSA
		    stm #0001H,DMSDN                 ;set element address index to +1
		    stm #0000001010000010b,DMPREC
		    ;    0---------------:(FREE)     DMA stops on emulation stop
		    ;    ------1---------:(DPRC[1])  Channel 1 high priority
		    ;    --------10------:(INTOSEL)  7bit,DMA1 INT;  10bit,DMA2 INT;  11bit,DMA3 INT
		    ;    --------------1-:(DE[1])    Channel 1 enabled 
		    
		    																								
			stm SPCR20,SPSA0
			ldm SPSD0,A
			or #0040h,A                         ;FRST=1,GRST=1;
			stl A,SPSD0
				
	        nop
	        nop
	        
	        						
			ldm SPSD0,A
			or #0001h,A                         ;XRST=1,enable 
			stl A,SPSD0
			stm SPCR10,SPSA0
			ldm SPSD0,A
			or #0001h,A                         ;RRST=1,enable
			stl A,SPSD0
			stm SPCR20,SPSA0
			ldm SPSD0,A
			or #0080h,A                         ;FRST=1
			stl A,SPSD0		
		    nop
		    nop
		    
		     
			POPD ST1
			POPD ST0
			ret
			.end