📄 fw.ls1
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202 PUBLIC main
203
---- 204 RSEG ?DT?main?FW
0000 205 ?main?BYTE:
0000 206 i?040: DS 4
0004 207 DevDescrLen?042: DS 4
0008 208 j?043: DS 4
000C 209 IntDescrAddr?044: DS 2
000E 210 ExtDescrAddr?045: DS 2
211
---- 212 RSEG ?BI?FW
0000 213 Rwuen: DBIT 1
0001 214 GotSUD: DBIT 1
0002 215 Selfpwr: DBIT 1
0003 216 Sleep: DBIT 1
217
---- 218 RSEG ?DT?FW
0000 219 pHighSpeedConfigDscr: DS 2
0002 220 pDeviceDscr: DS 2
0004 221 pConfigDscr: DS 2
0006 222 pOtherConfigDscr: DS 2
0008 223 pFullSpeedConfigDscr: DS 2
000A 224 pDeviceQualDscr: DS 2
000C 225 pStringDscr: DS 2
226
---- 227 RSEG ?CO?FW
0000 228 EPCS_Offset_Lookup_Table:
0000 00 229 DB 000H
0001 01 230 DB 001H
0002 02 231 DB 002H
0003 02 232 DB 002H
0004 03 233 DB 003H
0005 03 234 DB 003H
0006 04 235 DB 004H
0007 04 236 DB 004H
0008 05 237 DB 005H
0009 05 238 DB 005H
239
240 ; //-----------------------------------------------------------------------------
241 ; // File: fw.c
242 ; // Contents: Firmware frameworks task dispatcher and device request parser
243 ; // source.
244 ; //
245 ; // indent 3. NO TABS!
246 ; //
247 ; // $Revision: 18 $
248 ; // $Date: 12/04/01 5:33p $
249 ; //
250 ; // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
251 ; //-----------------------------------------------------------------------------
252 ; #include "fx2.h"
253 ; #include "fx2regs.h"
254 ;
255 ; //-----------------------------------------------------------------------------
256 ; // Constants
A51 MACRO ASSEMBLER FW 12/29/2005 11:19:53 PAGE 5
257 ; //-----------------------------------------------------------------------------
258 ; #define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48
259 ; #define _IFREQ 48000 // IFCLK constant for Synchronization Delay
260 ; #define _CFREQ 48000 // CLKOUT constant for Synchronization Delay
261 ;
262 ; //-----------------------------------------------------------------------------
263 ; // Random Macros
264 ; //-----------------------------------------------------------------------------
265 ; #define min(a,b) (((a)<(b))?(a):(b))
266 ; #define max(a,b) (((a)>(b))?(a):(b))
267 ;
268 ; // Registers which require a synchronization delay, see section 15.14
269 ; // FIFORESET FIFOPINPOLAR
270 ; // INPKTEND OUTPKTEND
271 ; // EPxBCH:L REVCTL
272 ; // GPIFTCB3 GPIFTCB2
273 ; // GPIFTCB1 GPIFTCB0
274 ; // EPxFIFOPFH:L EPxAUTOINLENH:L
275 ; // EPxFIFOCFG EPxGPIFFLGSEL
276 ; // PINFLAGSxx EPxFIFOIRQ
277 ; // EPxFIFOIE GPIFIRQ
278 ; // GPIFIE GPIFADRH:L
279 ; // UDMACRCH:L EPxGPIFTRIG
280 ; // GPIFTRIG
281 ;
282 ; // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
283 ; // ...these have been replaced by GPIFTC[B3:B0] registers
284 ;
285 ; #include "fx2sdly.h" // Define _IFREQ and _CFREQ above this #include
286 ;
287 ; //-----------------------------------------------------------------------------
288 ; // Global Variables
289 ; //-----------------------------------------------------------------------------
290 ; volatile BOOL GotSUD;
291 ; BOOL Rwuen;
292 ; BOOL Selfpwr;
293 ; volatile BOOL Sleep; // Sleep mode enable flag
294 ;
295 ; WORD pDeviceDscr; // Pointer to Device Descriptor; Descriptors may be moved
296 ; WORD pDeviceQualDscr;
297 ; WORD pHighSpeedConfigDscr;
298 ; WORD pFullSpeedConfigDscr;
299 ; WORD pConfigDscr;
300 ; WORD pOtherConfigDscr;
301 ; WORD pStringDscr;
302 ;
303 ; //-----------------------------------------------------------------------------
304 ; // Prototypes
305 ; //-----------------------------------------------------------------------------
306 ; void SetupCommand(void);
307 ; void TD_Init(void);
308 ; void TD_Poll(void);
309 ; BOOL TD_Suspend(void);
310 ; BOOL TD_Resume(void);
311 ;
312 ; BOOL DR_GetDescriptor(void);
313 ; BOOL DR_SetConfiguration(void);
314 ; BOOL DR_GetConfiguration(void);
315 ; BOOL DR_SetInterface(void);
316 ; BOOL DR_GetInterface(void);
317 ; BOOL DR_GetStatus(void);
318 ; BOOL DR_ClearFeature(void);
319 ; BOOL DR_SetFeature(void);
320 ; BOOL DR_VendorCmnd(void);
321 ;
322 ; // this table is used by the epcs macro
A51 MACRO ASSEMBLER FW 12/29/2005 11:19:53 PAGE 6
323 ; const char code EPCS_Offset_Lookup_Table[] =
324 ; {
325 ; 0, // EP1OUT
326 ; 1, // EP1IN
327 ; 2, // EP2OUT
328 ; 2, // EP2IN
329 ; 3, // EP4OUT
330 ; 3, // EP4IN
331 ; 4, // EP6OUT
332 ; 4, // EP6IN
333 ; 5, // EP8OUT
334 ; 5, // EP8IN
335 ; };
336 ;
337 ; // macro for generating the address of an endpoint's control and status register (EPnCS)
338 ; #define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1)
339 ;
340 ; //-----------------------------------------------------------------------------
341 ; // Code
342 ; //-----------------------------------------------------------------------------
343 ;
344 ; // Task dispatcher
345 ; void main(void)
346
---- 347 RSEG ?PR?main?FW
0000 348 main:
349 USING 0
350 ; SOURCE LINE # 106
351 ; {
352 ; SOURCE LINE # 107
353 ; DWORD i;
354 ; WORD offset;
355 ; DWORD DevDescrLen;
356 ; DWORD j=0;
357 ; SOURCE LINE # 111
0000 E4 358 CLR A
0001 F500 F 359 MOV j?043+03H,A
0003 F500 F 360 MOV j?043+02H,A
0005 F500 F 361 MOV j?043+01H,A
0007 F500 F 362 MOV j?043,A
363 ; WORD IntDescrAddr;
364 ; WORD ExtDescrAddr;
365 ;
366 ; // Initialize Global States
367 ; Sleep = FALSE; // Disable sleep mode
368 ; SOURCE LINE # 116
0009 C200 F 369 CLR Sleep
370 ; Rwuen = FALSE; // Disable remote wakeup
371 ; SOURCE LINE # 117
000B C200 F 372 CLR Rwuen
373 ; Selfpwr = FALSE; // Disable self powered
374 ; SOURCE LINE # 118
000D C200 F 375 CLR Selfpwr
376 ; GotSUD = FALSE; // Clear "Got setup data" flag
377 ; SOURCE LINE # 119
000F C200 F 378 CLR GotSUD
379 ;
380 ; // Initialize user device
381 ; TD_Init();
382 ; SOURCE LINE # 122
0011 120000 F 383 LCALL TD_Init
384 ;
385 ; // The following section of code is used to relocate the descriptor table.
386 ; // Since the SUDPTRH and SUDPTRL are assigned the address of the descriptor
387 ; // table, the descriptor table must be located in on-part memory.
388 ; // The 4K demo tools locate all code sections in external memory.
A51 MACRO ASSEMBLER FW 12/29/2005 11:19:53 PAGE 7
389 ; // The descriptor table is relocated by the frameworks ONLY if it is found
390 ; // to be located in external memory.
391 ; pDeviceDscr = (WORD)&DeviceDscr;
392 ; SOURCE LINE # 130
0014 7E00 F 393 MOV R6,#HIGH (DeviceDscr)
0016 7F00 F 394 MOV R7,#LOW (DeviceDscr)
0018 8E00 F 395 MOV pDeviceDscr,R6
001A 8F00 F 396 MOV pDeviceDscr+01H,R7
397 ; pDeviceQualDscr = (WORD)&DeviceQualDscr;
398 ; SOURCE LINE # 131
001C 750000 F 399 MOV pDeviceQualDscr,#HIGH (DeviceQualDscr)
001F 750000 F 400 MOV pDeviceQualDscr+01H,#LOW (DeviceQualDscr)
401 ; pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr;
402 ; SOURCE LINE # 132
0022 750000 F 403 MOV pHighSpeedConfigDscr,#HIGH (HighSpeedConfigDscr)
0025 750000 F 404 MOV pHighSpeedConfigDscr+01H,#LOW (HighSpeedConfigDscr)
405 ; pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr;
406 ; SOURCE LINE # 133
0028 750000 F 407 MOV pFullSpeedConfigDscr,#HIGH (FullSpeedConfigDscr)
002B 750000 F 408 MOV pFullSpeedConfigDscr+01H,#LOW (FullSpeedConfigDscr)
409 ; pStringDscr = (WORD)&StringDscr;
410 ; SOURCE LINE # 134
002E 750000 F 411 MOV pStringDscr,#HIGH (StringDscr)
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