bulkloop.c

提供了usb接口fx2芯片的编程。从io输入到后来的差分信号输出。都给了详细的例子

#pragma NOIV               // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
//   File:      bulkloop.c
//   Contents:   Hooks required to implement USB peripheral function.
//
//   Copyright (c) 2000 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h"            // SYNCDELAY macro

extern BOOL GotSUD;             // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration;             // Current configuration
BYTE AlternateSetting;          // Alternate settings
BYTE Writedoneflag = 1;
BYTE   Highspeed = 0;
WORD xfrcnt = 64;
sbit xfr_ctl = IOA ^ 0;
sbit stu1 =    IOA ^ 1;
sbit stu2 =    IOA ^ 2;
sbit wr_ack =  IOA ^ 3;

#define VR_NAKALL_ON    0xD0    //制造商请求
#define VR_NAKALL_OFF   0xD1
#define SINGLEWRITE     0xB1 
#define SINGLEREAD      0xB2
#define GETSPEED        0xB3
#define FWUPDATA        0xB4
#define DWWRITE         0xB5


  WORD j;
  BYTE rddr;
  BYTE AD;
  BYTE D16;
  WORD i;

void rddata(BYTE AD);
void rddata16(BYTE AD);


//-----------------------------------------------------------------------------
// Task Dispatcher hooks
//   The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------

void TD_Init(void)             // Called once at startup
{  
   // set the CPU clock to 48MHz
  // CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
   CPUCS = 0x30;
   SYNCDELAY;
   
   // set the slave FIFO interface to 48MHz
 //  IFCONFIG |= 0x40;
   //OEB|=0xFF    //

  // Registers which require a synchronization delay, see section 15.14
  // FIFORESET        FIFOPINPOLAR
  // INPKTEND         OUTPKTEND
  // EPxBCH:L         REVCTL
  // GPIFTCB3         GPIFTCB2
  // GPIFTCB1         GPIFTCB0
  // EPxFIFOPFH:L     EPxAUTOINLENH:L
  // EPxFIFOCFG       EPxGPIFFLGSEL
  // PINFLAGSxx       EPxFIFOIRQ
  // EPxFIFOIE        GPIFIRQ
  // GPIFIE           GPIFADRH:L
  // UDMACRCH:L       EPxGPIFTRIG
  // GPIFTRIG
  
  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
  //      ...these have been replaced by GPIFTC[B3:B0] registers

  // default: all endpoints have their VALID bit set
  // default: TYPE1 = 1 and TYPE0 = 0 --> BULK  
  // default: EP2 and EP4 DIR bits are 0 (OUT direction)
  // default: EP6 and EP8 DIR bits are 1 (IN direction)
  // default: EP2, EP4, EP6, and EP8 are double buffered

  // we are just using the default values, yes this is not necessary...
  EP1OUTCFG = 0xA0;
  SYNCDELAY;
  EP1INCFG = 0xA0;
  SYNCDELAY;                    // see TRM section 15.14
  EP2CFG = 0xA0;
  SYNCDELAY;                    
  EP4CFG = 0xA0;
  SYNCDELAY;                    
  EP6CFG = 0xE2;
  SYNCDELAY;                    
  EP8CFG = 0xE0;

  // out endpoints do not come up armed
  
  // since the defaults are double buffered we must write dummy byte counts twice
  SYNCDELAY;                    
  EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
  SYNCDELAY;                    
  EP2BCL = 0x80;
  SYNCDELAY;               
  EP2BCL = 0x80;                
  SYNCDELAY;                    
  EP2BCL = 0x80;

  SYNCDELAY;                 
  EP4BCL = 0x80;                // arm EP4OUT by writing byte count w/skip.
  SYNCDELAY;                    
  EP4BCL = 0x80;    

  // enable dual autopointer feature
  AUTOPTRSETUP |= 0x01;
  SYNCDELAY;
  PORTACFG = 0x00; 
  
  OEA |= 0xF7;
  OEB |= 0xFF;
  OED |= 0XFF;
  OEE |= 0XFF;
  stu1 = 0;
  stu2 = 1;
  xfr_ctl = 0;
  Rwuen = TRUE;                 // Enable remote-wakeup
//  EPIE=0x10;
}


void TD_Poll(void)              // Called repeatedly while the device is idle
{
  BYTE i;
  BYTE k;
  BYTE tmp;
  BYTE tmp1;
  BYTE tmp2;
  BYTE tmp3 = 0;
  WORD count;
   if(!(EP2468STAT & bmEP2EMPTY))
    {
	    Writedoneflag = 0;
        count = (EP2BCH << 8) + EP2BCL;
        for(k = 0;k<(count/4);k++)
        {
	      for(j = 0;j < 4;j++)
		  {
           tmp1 = EP2FIFOBUF[4*k+j];
		 
		   for(i=0;i<4;i++)
		   {
		   tmp2 = ((tmp1)&(1<<i));
		   tmp3 |= (tmp2)<<(7-(i<<1));
		   }
		   for(i=4;i<8;i++)
		   {
		   tmp2 = ((tmp1)&(1<<i));
		   tmp3 |= (tmp2)>>((i<<1)-7);
		   }

		   IOB = tmp3;
		   xfr_ctl = 1;
		   while(wr_ack !=1);
		   xfr_ctl = 0;
		   tmp3 = 0;
		  }
         }
		 EP2BCL = 0x80;
   }
	    
}                                                                                                                                                                       
                                                                                                                                                                         
 BOOL TD_Suspend(void)          // Called before the device goes into suspend mode                                                                                       
 {                                                                                                                                                                       
    return(TRUE);                                                                                                                                                        
 }                                                                                                                                                                       
                                                                                                                                                                         
 BOOL TD_Resume(void)          // Called after the device resumes                                                                                                        
 {                                                                                                                                                                       
    return(TRUE);                                                                                                                                                        
 }                                                                                                                                                                       
                                                                                                                                                                         
  //-----------------------------------------------------------------------------                                                                                        
 // Device Request hooks                                                                                                                                                 
 
 
 
 

//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------

BOOL DR_GetDescriptor(void)
{
   return(TRUE);
}

BOOL DR_SetConfiguration(void)   // Called when a Set Configuration command is received
{
   Configuration = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received
{
   EP0BUF[0] = Configuration;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_SetInterface(void)       // Called when a Set Interface command is received
{
   AlternateSetting = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetInterface(void)       // Called when a Set Interface command is received
{
   EP0BUF[0] = AlternateSetting;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_GetStatus(void)
{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}

BOOL DR_VendorCmnd(void)
{
  BYTE tmp;
  BYTE tmp1;
  BYTE tmp2;
  BYTE tmp3 = 0;
  BYTE i;
  
  switch (SETUPDAT[1])
  {
     case VR_NAKALL_ON:
        tmp = FIFORESET;
        tmp |= bmNAKALL;      
        SYNCDELAY;                    
        FIFORESET = tmp;
        break;
     case VR_NAKALL_OFF:
        tmp = FIFORESET;
        tmp &= ~bmNAKALL;      
        SYNCDELAY;                    
        FIFORESET = tmp;
        break;
     case SINGLEWRITE:    //single write,data in SETUPDAT[2],ram address in SETUPDAT[4]
	      
          tmp1 = SETUPDAT[2];
		 
		  for(i=0;i<4;i++)
		  {
		   tmp2 = ((tmp1)&(1<<i));
		   tmp3 |= (tmp2)<<(7-(i<<1));
		   //tmp3 = 0x40;
		  }
		  for(i=4;i<8;i++)
		  {
		   tmp2 = ((tmp1)&(1<<i));
		   tmp3 |= (tmp2)>>((i<<1)-7);
		   //tmp3 = 0x40;
		  }

		  IOB = tmp3;
		  xfr_ctl = 1;
          //tmp = SETUPDAT[2];
		  while(wr_ack !=1);
		  xfr_ctl = 0;
		    
          EP0BUF[0] = SETUPDAT[4];  //随便返回一个值，用于测试   
          //EP0BUF[5] = tmp;
                                       
		  EP0BCH = 0;        //这两句保留      
          SYNCDELAY;                          
		  EP0BCL = 8;
          break;                                
     case SINGLEREAD:         //single read,ram address in SETUPDAT[4],put the data in EP0BUF[0]
          OEC &= 0x00; 
          IOB = SETUPDAT[4];
          EP0BUF[0] = IOC;
          EP0BCH = 0;        //这两句保留
		  EP0BCL = 8; 
          break; 
     case GETSPEED:
         if(Highspeed==1)
           {
             xfrcnt = 512;
           }
         else xfrcnt = 64;
         //EP0BUF[0] = Highspeed;
         EP0BUF[0] = 8;
         EP0BUF[1] = xfrcnt>>8;
         EP0BUF[2] = (BYTE)xfrcnt;