📄 fw.lst
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474 =1 sbit EIPX6 = 0xF8+4;
475 =1
476 =1 /*-----------------------------------------------------------------------------
477 =1 Bit Masks
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 15
478 =1 -----------------------------------------------------------------------------*/
479 =1
480 =1 /* CPU Control & Status Register (CPUCS) */
481 =1 #define bmPRTCSTB bmBIT5
482 =1 #define bmCLKSPD (bmBIT4 | bmBIT3)
483 =1 #define bmCLKSPD1 bmBIT4
484 =1 #define bmCLKSPD0 bmBIT3
485 =1 #define bmCLKINV bmBIT2
486 =1 #define bmCLKOE bmBIT1
487 =1 #define bm8051RES bmBIT0
488 =1 /* Port Alternate Configuration Registers */
489 =1 /* Port A (PORTACFG) */
490 =1 #define bmFLAGD bmBIT7
491 =1 #define bmINT1 bmBIT1
492 =1 #define bmINT0 bmBIT0
493 =1 /* Port C (PORTCCFG) */
494 =1 #define bmGPIFA7 bmBIT7
495 =1 #define bmGPIFA6 bmBIT6
496 =1 #define bmGPIFA5 bmBIT5
497 =1 #define bmGPIFA4 bmBIT4
498 =1 #define bmGPIFA3 bmBIT3
499 =1 #define bmGPIFA2 bmBIT2
500 =1 #define bmGPIFA1 bmBIT1
501 =1 #define bmGPIFA0 bmBIT0
502 =1 /* Port E (PORTECFG) */
503 =1 #define bmGPIFA8 bmBIT7
504 =1 #define bmT2EX bmBIT6
505 =1 #define bmINT6 bmBIT5
506 =1 #define bmRXD1OUT bmBIT4
507 =1 #define bmRXD0OUT bmBIT3
508 =1 #define bmT2OUT bmBIT2
509 =1 #define bmT1OUT bmBIT1
510 =1 #define bmT0OUT bmBIT0
511 =1
512 =1 /* I2C Control & Status Register (I2CS) */
513 =1 #define bmSTART bmBIT7
514 =1 #define bmSTOP bmBIT6
515 =1 #define bmLASTRD bmBIT5
516 =1 #define bmID (bmBIT4 | bmBIT3)
517 =1 #define bmBERR bmBIT2
518 =1 #define bmACK bmBIT1
519 =1 #define bmDONE bmBIT0
520 =1 /* I2C Control Register (I2CTL) */
521 =1 #define bmSTOPIE bmBIT1
522 =1 #define bm400KHZ bmBIT0
523 =1 /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
524 =1 #define bmIV4 bmBIT6
525 =1 #define bmIV3 bmBIT5
526 =1 #define bmIV2 bmBIT4
527 =1 #define bmIV1 bmBIT3
528 =1 #define bmIV0 bmBIT2
529 =1 /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
530 =1 #define bmEP0ACK bmBIT6
531 =1 #define bmHSGRANT bmBIT5
532 =1 #define bmURES bmBIT4
533 =1 #define bmSUSP bmBIT3
534 =1 #define bmSUTOK bmBIT2
535 =1 #define bmSOF bmBIT1
536 =1 #define bmSUDAV bmBIT0
537 =1 /* Breakpoint register (BREAKPT) */
538 =1 #define bmBREAK bmBIT3
539 =1 #define bmBPPULSE bmBIT2
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 16
540 =1 #define bmBPEN bmBIT1
541 =1 /* Interrupt 2 & 4 Setup (INTSETUP) */
542 =1 #define bmAV2EN bmBIT3
543 =1 #define INT4IN bmBIT1
544 =1 #define bmAV4EN bmBIT0
545 =1 /* USB Control & Status Register (USBCS) */
546 =1 #define bmHSM bmBIT7
547 =1 #define bmDISCON bmBIT3
548 =1 #define bmNOSYNSOF bmBIT2
549 =1 #define bmRENUM bmBIT1
550 =1 #define bmSIGRESUME bmBIT0
551 =1 /* Wakeup Control and Status Register (WAKEUPCS) */
552 =1 #define bmWU2 bmBIT7
553 =1 #define bmWU bmBIT6
554 =1 #define bmWU2POL bmBIT5
555 =1 #define bmWUPOL bmBIT4
556 =1 #define bmDPEN bmBIT2
557 =1 #define bmWU2EN bmBIT1
558 =1 #define bmWUEN bmBIT0
559 =1 /* End Point 0 Control & Status Register (EP0CS) */
560 =1 #define bmHSNAK bmBIT7
561 =1 /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
562 =1 #define bmEPBUSY bmBIT1
563 =1 #define bmEPSTALL bmBIT0
564 =1 /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
565 =1 #define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
566 =1 #define bmEPFULL bmBIT3
567 =1 #define bmEPEMPTY bmBIT2
568 =1 /* Endpoint Status (EP2468STAT) SFR bits */
569 =1 #define bmEP8FULL bmBIT7
570 =1 #define bmEP8EMPTY bmBIT6
571 =1 #define bmEP6FULL bmBIT5
572 =1 #define bmEP6EMPTY bmBIT4
573 =1 #define bmEP4FULL bmBIT3
574 =1 #define bmEP4EMPTY bmBIT2
575 =1 #define bmEP2FULL bmBIT1
576 =1 #define bmEP2EMPTY bmBIT0
577 =1 /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
578 =1 #define bmSDPAUTO bmBIT0
579 =1 /* Endpoint Data Toggle Control (TOGCTL) */
580 =1 #define bmQUERYTOGGLE bmBIT7
581 =1 #define bmSETTOGGLE bmBIT6
582 =1 #define bmRESETTOGGLE bmBIT5
583 =1 #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
584 =1 /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
585 =1 #define bmEP8IBN bmBIT5
586 =1 #define bmEP6IBN bmBIT4
587 =1 #define bmEP4IBN bmBIT3
588 =1 #define bmEP2IBN bmBIT2
589 =1 #define bmEP1IBN bmBIT1
590 =1 #define bmEP0IBN bmBIT0
591 =1
592 =1 /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
593 =1 #define bmEP8PING bmBIT7
594 =1 #define bmEP6PING bmBIT6
595 =1 #define bmEP4PING bmBIT5
596 =1 #define bmEP2PING bmBIT4
597 =1 #define bmEP1PING bmBIT3
598 =1 #define bmEP0PING bmBIT2
599 =1 #define bmIBN bmBIT0
600 =1
601 =1 /* Interface Configuration bits (IFCONFIG) */
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 17
602 =1 #define bmIFCLKSRC bmBIT7
603 =1 #define bm3048MHZ bmBIT6
604 =1 #define bmIFCLKOE bmBIT5
605 =1 #define bmIFCLKPOL bmBIT4
606 =1 #define bmASYNC bmBIT3
607 =1 #define bmGSTATE bmBIT2
608 =1 #define bmIFCFG1 bmBIT1
609 =1 #define bmIFCFG0 bmBIT0
610 =1 #define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
611 =1 #define bmIFGPIF bmIFCFG1
612 =1
613 =1 /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
614 =1 #define bmINFM bmBIT6
615 =1 #define bmOEP bmBIT5
616 =1 #define bmAUTOOUT bmBIT4
617 =1 #define bmAUTOIN bmBIT3
618 =1 #define bmZEROLENIN bmBIT2
619 =1 #define bmWORDWIDE bmBIT0
620 =1
621 =1 /* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
622 =1 features */
623 =1 #define bmNOAUTOARM bmBIT1
624 =1 #define bmSKIPCOMMIT bmBIT0
625 =1
626 =1 /* Fifo Reset bits (FIFORESET) */
627 =1 #define bmNAKALL bmBIT7
628 =1
629 =1 #endif /* FX2REGS_H */
15
16 //-----------------------------------------------------------------------------
17 // Constants
18 //-----------------------------------------------------------------------------
19 #define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48
20 #define _IFREQ 48000 // IFCLK constant for Synchronization Delay
21 #define _CFREQ 48000 // CLKOUT constant for Synchronization Delay
22
23 //-----------------------------------------------------------------------------
24 // Random Macros
25 //-----------------------------------------------------------------------------
26 #define min(a,b) (((a)<(b))?(a):(b))
27 #define max(a,b) (((a)>(b))?(a):(b))
28
29 // Registers which require a synchronization delay, see section 15.14
30 // FIFORESET FIFOPINPOLAR
31 // INPKTEND OUTPKTEND
32 // EPxBCH:L REVCTL
33 // GPIFTCB3 GPIFTCB2
34 // GPIFTCB1 GPIFTCB0
35 // EPxFIFOPFH:L EPxAUTOINLENH:L
36 // EPxFIFOCFG EPxGPIFFLGSEL
37 // PINFLAGSxx EPxFIFOIRQ
38 // EPxFIFOIE GPIFIRQ
39 // GPIFIE GPIFADRH:L
40 // UDMACRCH:L EPxGPIFTRIG
41 // GPIFTRIG
42
43 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
44 // ...these have been replaced by GPIFTC[B3:B0] registers
45
46 #include "fx2sdly.h" // Define _IFREQ and _CFREQ above this #include
1 =1 //-----------------------------------------------------------------------------
2 =1 // File: fx2sdly.h
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 18
3 =1 // Contents: EZ-USB FX2 Synchronization Delay (SYNCDELAY) Macro
4 =1 //
5 =1 // Enter with _IFREQ = IFCLK in kHz
6 =1 // Enter with _CFREQ = CLKOUT in kHz
7 =1 //
8 =1 // Copyright (c) 2001 Cypress Semiconductor, All rights reserved
9 =1 //-----------------------------------------------------------------------------
10 =1 #include "intrins.h"
1 =2 /*--------------------------------------------------------------------------
2 =2 INTRINS.H
3 =2
4 =2 Intrinsic functions for C51.
5 =2 Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
6 =2 All rights reserved.
7 =2 --------------------------------------------------------------------------*/
8 =2
9 =2 #ifndef __INTRINS_H__
10 =2 #define __INTRINS_H__
11 =2
12 =2 extern void _nop_ (void);
13 =2 extern bit _testbit_ (⌨️ 快捷键说明
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