📄 fw.src
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; .\fw.SRC generated from: fw.c
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\C51.EXE fw.c BROWSE DEBUG OBJECTEXTEND LISTINCLUDE SRC(.\fw.SRC)
$NOMOD51
NAME FW
TB81 BIT 0C0H.3
INT2CLR DATA 0A1H
SM01 BIT 0C0H.7
SM11 BIT 0C0H.6
INT4CLR DATA 0A2H
EI2C BIT 0E8H.1
AC BIT 0D0H.6
SM21 BIT 0C0H.5
EA BIT 0A8H.7
APTR1FZ BIT 0B0H.0
APTR2FZ BIT 0B0H.1
IE DATA 0A8H
DPH1 DATA 085H
PI2C BIT 0F8H.1
GPIFSGLDATLX DATA 0BEH
FL BIT 0D0H.1
DPL1 DATA 084H
EXF2 BIT 0C8H.6
REN1 BIT 0C0H.4
IP DATA 0B8H
RI BIT 098H.0
CY BIT 0D0H.7
TI BIT 098H.1
SPC_FNC DATA 08FH
INT6 BIT 0D8H.3
RCAP2H DATA 0CBH
SP DATA 081H
OV BIT 0D0H.2
RCAP2L DATA 0CAH
C_T2 BIT 0C8H.1
EP2468STAT DATA 0AAH
AUTOPTR1H DATA 09AH
RCLK BIT 0C8H.5
GPIFSGLDATLNOX DATA 0BFH
AUTOPTRH2 DATA 09DH
EXIF DATA 091H
TCLK BIT 0C8H.4
EUSB BIT 0E8H.0
AUTOPTR1L DATA 09BH
AUTOPTRL2 DATA 09EH
PCON DATA 087H
GPIFSGLDATH DATA 0BDH
APTR1H DATA 09AH
RESI BIT 0D8H.4
EP01STAT DATA 0BAH
TMOD DATA 089H
TCON DATA 088H
APTR1L DATA 09BH
EXTACC BIT 0A8H.7
PUSB BIT 0F8H.0
IE0 BIT 088H.1
IE1 BIT 088H.3
B DATA 0F0H
CP_RL2 BIT 0C8H.0
AUTOPTRSETUP DATA 0AFH
ACC DATA 0E0H
ES0 BIT 0A8H.4
ES1 BIT 0A8H.6
ET0 BIT 0A8H.1
ET1 BIT 0A8H.3
TF0 BIT 088H.5
ET2 BIT 0A8H.5
TF1 BIT 088H.7
TF2 BIT 0C8H.7
RI1 BIT 0C0H.0
RB8 BIT 098H.2
TH0 DATA 08CH
EX0 BIT 0A8H.0
TH1 DATA 08DH
IT0 BIT 088H.0
TH2 DATA 0CDH
TI1 BIT 0C0H.1
EX1 BIT 0A8H.2
TB8 BIT 098H.3
IT1 BIT 088H.2
P BIT 0D0H.0
EP24FIFOFLGS DATA 0ABH
SM0 BIT 098H.7
TL0 DATA 08AH
SM1 BIT 098H.6
TL1 DATA 08BH
TL2 DATA 0CCH
SM2 BIT 098H.5
EIE DATA 0E8H
PS0 BIT 0B8H.4
PS1 BIT 0B8H.6
PT0 BIT 0B8H.1
RS0 BIT 0D0H.3
PT1 BIT 0B8H.3
OEA DATA 0B2H
RS1 BIT 0D0H.4
PT2 BIT 0B8H.5
OEB DATA 0B3H
TR0 BIT 088H.4
OEC DATA 0B4H
TR1 BIT 088H.6
TR2 BIT 0C8H.2
PX0 BIT 0B8H.0
OED DATA 0B5H
EP68FIFOFLGS DATA 0ACH
PX1 BIT 0B8H.2
OEE DATA 0B6H
IOA DATA 080H
IOB DATA 090H
IOC DATA 0A0H
IOD DATA 0B0H
DPH DATA 083H
IOE DATA 0B1H
EIP DATA 0F8H
GPIFTRIG DATA 0BBH
EIEX4 BIT 0E8H.2
DPL DATA 082H
EIEX5 BIT 0E8H.3
SBUF0 DATA 099H
EIEX6 BIT 0E8H.4
SBUF1 DATA 0C1H
EXEN2 BIT 0C8H.3
SCON0 DATA 098H
SEL BIT 080H.6
SMOD1 BIT 0D8H.7
SCON1 DATA 0C0H
REN BIT 098H.4
T2CON DATA 0C8H
DPS DATA 086H
EIPX4 BIT 0F8H.2
MPAGE DATA 092H
EIPX5 BIT 0F8H.3
EIPX6 BIT 0F8H.4
EICON DATA 0D8H
CKCON DATA 08EH
F0 BIT 0D0H.5
ERESI BIT 0D8H.5
PSW DATA 0D0H
RB81 BIT 0C0H.2
?PR?main?FW SEGMENT CODE
?DT?main?FW SEGMENT DATA OVERLAYABLE
?PR?SetupCommand?FW SEGMENT CODE
?PR?resume_isr?FW SEGMENT CODE
?CO?FW SEGMENT CODE
?BI?FW SEGMENT BIT
?DT?FW SEGMENT DATA
EXTRN XDATA (INTSETUP)
EXTRN XDATA (USBCS)
EXTRN CODE (DR_SetConfiguration)
EXTRN CODE (StringDscr)
EXTRN CODE (TD_Init)
EXTRN CODE (TD_Poll)
EXTRN XDATA (EP0BCH)
EXTRN XDATA (EP0BCL)
EXTRN CODE (EZUSB_Susp)
EXTRN CODE (DR_GetStatus)
EXTRN XDATA (EP0BUF)
EXTRN XDATA (SUDPTRH)
EXTRN CODE (DR_GetInterface)
EXTRN CODE (UserDscr)
EXTRN XDATA (SUDPTRL)
EXTRN CODE (DR_ClearFeature)
EXTRN CODE (DR_SetInterface)
EXTRN CODE (DR_GetDescriptor)
EXTRN XDATA (TOGCTL)
EXTRN CODE (EZUSB_Discon)
EXTRN BIT (?EZUSB_Discon?BIT)
EXTRN XDATA (EP0CS)
EXTRN CODE (TD_Suspend)
EXTRN CODE (EZUSB_Resume)
EXTRN CODE (HighSpeedConfigDscr)
EXTRN CODE (DeviceDscr)
EXTRN XDATA (WAKEUPCS)
EXTRN CODE (DR_VendorCmnd)
EXTRN CODE (TD_Resume)
EXTRN XDATA (SETUPDAT)
EXTRN CODE (FullSpeedConfigDscr)
EXTRN CODE (DR_SetFeature)
EXTRN CODE (_EZUSB_GetStringDscr)
EXTRN CODE (DeviceQualDscr)
EXTRN XDATA (USBIE)
EXTRN CODE (DR_GetConfiguration)
EXTRN CODE (?C_STARTUP)
EXTRN CODE (?C?ULCMP)
PUBLIC Sleep
PUBLIC pStringDscr
PUBLIC pDeviceQualDscr
PUBLIC Selfpwr
PUBLIC pFullSpeedConfigDscr
PUBLIC pOtherConfigDscr
PUBLIC pConfigDscr
PUBLIC pDeviceDscr
PUBLIC pHighSpeedConfigDscr
PUBLIC GotSUD
PUBLIC Rwuen
PUBLIC EPCS_Offset_Lookup_Table
PUBLIC resume_isr
PUBLIC SetupCommand
PUBLIC main
RSEG ?DT?main?FW
?main?BYTE:
i?040: DS 4
DevDescrLen?042: DS 4
j?043: DS 4
IntDescrAddr?044: DS 2
ExtDescrAddr?045: DS 2
RSEG ?BI?FW
Rwuen: DBIT 1
GotSUD: DBIT 1
Selfpwr: DBIT 1
Sleep: DBIT 1
RSEG ?DT?FW
pHighSpeedConfigDscr: DS 2
pDeviceDscr: DS 2
pConfigDscr: DS 2
pOtherConfigDscr: DS 2
pFullSpeedConfigDscr: DS 2
pDeviceQualDscr: DS 2
pStringDscr: DS 2
RSEG ?CO?FW
EPCS_Offset_Lookup_Table:
DB 000H
DB 001H
DB 002H
DB 002H
DB 003H
DB 003H
DB 004H
DB 004H
DB 005H
DB 005H
; //-----------------------------------------------------------------------------
; // File: fw.c
; // Contents: Firmware frameworks task dispatcher and device request parser
; // source.
; //
; // indent 3. NO TABS!
; //
; // $Revision: 18 $
; // $Date: 12/04/01 5:33p $
; //
; // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
; //-----------------------------------------------------------------------------
; #include "fx2.h"
; #include "fx2regs.h"
;
; //-----------------------------------------------------------------------------
; // Constants
; //-----------------------------------------------------------------------------
; #define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48
; #define _IFREQ 48000 // IFCLK constant for Synchronization Delay
; #define _CFREQ 48000 // CLKOUT constant for Synchronization Delay
;
; //-----------------------------------------------------------------------------
; // Random Macros
; //-----------------------------------------------------------------------------
; #define min(a,b) (((a)<(b))?(a):(b))
; #define max(a,b) (((a)>(b))?(a):(b))
;
; // Registers which require a synchronization delay, see section 15.14
; // FIFORESET FIFOPINPOLAR
; // INPKTEND OUTPKTEND
; // EPxBCH:L REVCTL
; // GPIFTCB3 GPIFTCB2
; // GPIFTCB1 GPIFTCB0
; // EPxFIFOPFH:L EPxAUTOINLENH:L
; // EPxFIFOCFG EPxGPIFFLGSEL
; // PINFLAGSxx EPxFIFOIRQ
; // EPxFIFOIE GPIFIRQ
; // GPIFIE GPIFADRH:L
; // UDMACRCH:L EPxGPIFTRIG
; // GPIFTRIG
;
; // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
; // ...these have been replaced by GPIFTC[B3:B0] registers
;
; #include "fx2sdly.h" // Define _IFREQ and _CFREQ above this #include
;
; //-----------------------------------------------------------------------------
; // Global Variables
; //-----------------------------------------------------------------------------
; volatile BOOL GotSUD;
; BOOL Rwuen;
; BOOL Selfpwr;
; volatile BOOL Sleep; // Sleep mode enable flag
;
; WORD pDeviceDscr; // Pointer to Device Descriptor; Descriptors may be moved
; WORD pDeviceQualDscr;
; WORD pHighSpeedConfigDscr;
; WORD pFullSpeedConfigDscr;
; WORD pConfigDscr;
; WORD pOtherConfigDscr;
; WORD pStringDscr;
;
; //-----------------------------------------------------------------------------
; // Prototypes
; //-----------------------------------------------------------------------------
; void SetupCommand(void);
; void TD_Init(void);
; void TD_Poll(void);
; BOOL TD_Suspend(void);
; BOOL TD_Resume(void);
;
; BOOL DR_GetDescriptor(void);
; BOOL DR_SetConfiguration(void);
; BOOL DR_GetConfiguration(void);
; BOOL DR_SetInterface(void);
; BOOL DR_GetInterface(void);
; BOOL DR_GetStatus(void);
; BOOL DR_ClearFeature(void);
; BOOL DR_SetFeature(void);
; BOOL DR_VendorCmnd(void);
;
; // this table is used by the epcs macro
; const char code EPCS_Offset_Lookup_Table[] =
; {
; 0, // EP1OUT
; 1, // EP1IN
; 2, // EP2OUT
; 2, // EP2IN
; 3, // EP4OUT
; 3, // EP4IN
; 4, // EP6OUT
; 4, // EP6IN
; 5, // EP8OUT
; 5, // EP8IN
; };
;
; // macro for generating the address of an endpoint's control and status register (EPnCS)
; #define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1)
;
; //-----------------------------------------------------------------------------
; // Code
; //-----------------------------------------------------------------------------
;
; // Task dispatcher
; void main(void)
RSEG ?PR?main?FW
main:
USING 0
; SOURCE LINE # 106
; {
; SOURCE LINE # 107
; DWORD i;
; WORD offset;
; DWORD DevDescrLen;
; DWORD j=0;
; SOURCE LINE # 111
CLR A
MOV j?043+03H,A
MOV j?043+02H,A
MOV j?043+01H,A
MOV j?043,A
; WORD IntDescrAddr;
; WORD ExtDescrAddr;
;
; // Initialize Global States
; Sleep = FALSE; // Disable sleep mode
; SOURCE LINE # 116
CLR Sleep
; Rwuen = FALSE; // Disable remote wakeup
; SOURCE LINE # 117
CLR Rwuen
; Selfpwr = FALSE; // Disable self powered
; SOURCE LINE # 118
CLR Selfpwr
; GotSUD = FALSE; // Clear "Got setup data" flag
; SOURCE LINE # 119
CLR GotSUD
;
; // Initialize user device
; TD_Init();
; SOURCE LINE # 122
LCALL TD_Init
;
; // The following section of code is used to relocate the descriptor table.
; // Since the SUDPTRH and SUDPTRL are assigned the address of the descriptor
; // table, the descriptor table must be located in on-part memory.
; // The 4K demo tools locate all code sections in external memory.
; // The descriptor table is relocated by the frameworks ONLY if it is found
; // to be located in external memory.
; pDeviceDscr = (WORD)&DeviceDscr;
; SOURCE LINE # 130
MOV R6,#HIGH (DeviceDscr)
MOV R7,#LOW (DeviceDscr)
MOV pDeviceDscr,R6
MOV pDeviceDscr+01H,R7
; pDeviceQualDscr = (WORD)&DeviceQualDscr;
; SOURCE LINE # 131
MOV pDeviceQualDscr,#HIGH (DeviceQualDscr)
MOV pDeviceQualDscr+01H,#LOW (DeviceQualDscr)
; pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr;
; SOURCE LINE # 132
MOV pHighSpeedConfigDscr,#HIGH (HighSpeedConfigDscr)
MOV pHighSpeedConfigDscr+01H,#LOW (HighSpeedConfigDscr)
; pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr;
; SOURCE LINE # 133
MOV pFullSpeedConfigDscr,#HIGH (FullSpeedConfigDscr)
MOV pFullSpeedConfigDscr+01H,#LOW (FullSpeedConfigDscr)
; pStringDscr = (WORD)&StringDscr;
; SOURCE LINE # 134
MOV pStringDscr,#HIGH (StringDscr)
MOV pStringDscr+01H,#LOW (StringDscr)
;
; if ((WORD)&DeviceDscr & 0xe000)
; SOURCE LINE # 136
MOV A,R6
ANL A,#0E0H
JNZ $ + 5H
LJMP ?C0001
; {
; SOURCE LINE # 137
; IntDescrAddr = INTERNAL_DSCR_ADDR;
; SOURCE LINE # 138
MOV IntDescrAddr?044,#00H
MOV IntDescrAddr?044+01H,#080H
; ExtDescrAddr = (WORD)&DeviceDscr;
; SOURCE LINE # 139
MOV ExtDescrAddr?045,R6
MOV ExtDescrAddr?045+01H,R7
; DevDescrLen = (WORD)&UserDscr - (WORD)&DeviceDscr + 2;
; SOURCE LINE # 140
CLR C
MOV A,#LOW (UserDscr)
SUBB A,R7
MOV R7,A
MOV A,#HIGH (UserDscr)
SUBB A,R6
XCH A,R7
ADD A,#02H
XCH A,R7
ADDC A,#00H
MOV R6,A
CLR A
MOV DevDescrLen?042+03H,R7
MOV DevDescrLen?042+02H,R6
MOV DevDescrLen?042+01H,A
MOV DevDescrLen?042,A
; for (i = 0; i < DevDescrLen; i++)
; SOURCE LINE # 141
MOV i?040+03H,A
MOV i?040+02H,A
MOV i?040+01H,A
MOV i?040,A
?C0002:
MOV R7,DevDescrLen?042+03H
MOV R6,DevDescrLen?042+02H
MOV R5,DevDescrLen?042+01H
MOV R4,DevDescrLen?042
MOV R3,i?040+03H
MOV R2,i?040+02H
MOV R1,i?040+01H
MOV R0,i?040
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