lpm_rom0.fit.eqn

s盒设计源程序 可以用语DES设计

E1_q_b[7]_clock_1 = !GLOBAL(A1L51);
E1_q_b[7]_PORT_B_data_out = MEMORY(E1_q_b[7]_PORT_A_data_in_reg, E1_q_b[7]_PORT_B_data_in_reg, E1_q_b[7]_PORT_A_address_reg, E1_q_b[7]_PORT_B_address_reg, E1_q_b[7]_PORT_A_write_enable_reg, E1_q_b[7]_PORT_B_write_enable_reg, , , E1_q_b[7]_clock_0, E1_q_b[7]_clock_1, , , , );
E1_q_b[3] = E1_q_b[7]_PORT_B_data_out[4];

--E1_q_b[4] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[4] at M4K_X15_Y11
E1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
E1_q_b[7]_PORT_A_data_in_reg = DFFE(E1_q_b[7]_PORT_A_data_in, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_data_in = BUS(F1_ram_rom_data_reg[7], F1_ram_rom_data_reg[6], F1_ram_rom_data_reg[5], F1_ram_rom_data_reg[4], F1_ram_rom_data_reg[3], F1_ram_rom_data_reg[2], F1_ram_rom_data_reg[1], F1_ram_rom_data_reg[0]);
E1_q_b[7]_PORT_B_data_in_reg = DFFE(E1_q_b[7]_PORT_B_data_in, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[7]_PORT_A_address_reg = DFFE(E1_q_b[7]_PORT_A_address, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[7]_PORT_B_address_reg = DFFE(E1_q_b[7]_PORT_B_address, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_write_enable = GND;
E1_q_b[7]_PORT_A_write_enable_reg = DFFE(E1_q_b[7]_PORT_A_write_enable, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_write_enable = F1L2;
E1_q_b[7]_PORT_B_write_enable_reg = DFFE(E1_q_b[7]_PORT_B_write_enable, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_clock_0 = GLOBAL(clock);
E1_q_b[7]_clock_1 = !GLOBAL(A1L51);
E1_q_b[7]_PORT_B_data_out = MEMORY(E1_q_b[7]_PORT_A_data_in_reg, E1_q_b[7]_PORT_B_data_in_reg, E1_q_b[7]_PORT_A_address_reg, E1_q_b[7]_PORT_B_address_reg, E1_q_b[7]_PORT_A_write_enable_reg, E1_q_b[7]_PORT_B_write_enable_reg, , , E1_q_b[7]_clock_0, E1_q_b[7]_clock_1, , , , );
E1_q_b[4] = E1_q_b[7]_PORT_B_data_out[3];

--E1_q_b[5] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[5] at M4K_X15_Y11
E1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
E1_q_b[7]_PORT_A_data_in_reg = DFFE(E1_q_b[7]_PORT_A_data_in, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_data_in = BUS(F1_ram_rom_data_reg[7], F1_ram_rom_data_reg[6], F1_ram_rom_data_reg[5], F1_ram_rom_data_reg[4], F1_ram_rom_data_reg[3], F1_ram_rom_data_reg[2], F1_ram_rom_data_reg[1], F1_ram_rom_data_reg[0]);
E1_q_b[7]_PORT_B_data_in_reg = DFFE(E1_q_b[7]_PORT_B_data_in, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[7]_PORT_A_address_reg = DFFE(E1_q_b[7]_PORT_A_address, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[7]_PORT_B_address_reg = DFFE(E1_q_b[7]_PORT_B_address, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_write_enable = GND;
E1_q_b[7]_PORT_A_write_enable_reg = DFFE(E1_q_b[7]_PORT_A_write_enable, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_write_enable = F1L2;
E1_q_b[7]_PORT_B_write_enable_reg = DFFE(E1_q_b[7]_PORT_B_write_enable, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_clock_0 = GLOBAL(clock);
E1_q_b[7]_clock_1 = !GLOBAL(A1L51);
E1_q_b[7]_PORT_B_data_out = MEMORY(E1_q_b[7]_PORT_A_data_in_reg, E1_q_b[7]_PORT_B_data_in_reg, E1_q_b[7]_PORT_A_address_reg, E1_q_b[7]_PORT_B_address_reg, E1_q_b[7]_PORT_A_write_enable_reg, E1_q_b[7]_PORT_B_write_enable_reg, , , E1_q_b[7]_clock_0, E1_q_b[7]_clock_1, , , , );
E1_q_b[5] = E1_q_b[7]_PORT_B_data_out[2];

--E1_q_b[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[6] at M4K_X15_Y11
E1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
E1_q_b[7]_PORT_A_data_in_reg = DFFE(E1_q_b[7]_PORT_A_data_in, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_data_in = BUS(F1_ram_rom_data_reg[7], F1_ram_rom_data_reg[6], F1_ram_rom_data_reg[5], F1_ram_rom_data_reg[4], F1_ram_rom_data_reg[3], F1_ram_rom_data_reg[2], F1_ram_rom_data_reg[1], F1_ram_rom_data_reg[0]);
E1_q_b[7]_PORT_B_data_in_reg = DFFE(E1_q_b[7]_PORT_B_data_in, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[7]_PORT_A_address_reg = DFFE(E1_q_b[7]_PORT_A_address, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[7]_PORT_B_address_reg = DFFE(E1_q_b[7]_PORT_B_address, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_write_enable = GND;
E1_q_b[7]_PORT_A_write_enable_reg = DFFE(E1_q_b[7]_PORT_A_write_enable, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_write_enable = F1L2;
E1_q_b[7]_PORT_B_write_enable_reg = DFFE(E1_q_b[7]_PORT_B_write_enable, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_clock_0 = GLOBAL(clock);
E1_q_b[7]_clock_1 = !GLOBAL(A1L51);
E1_q_b[7]_PORT_B_data_out = MEMORY(E1_q_b[7]_PORT_A_data_in_reg, E1_q_b[7]_PORT_B_data_in_reg, E1_q_b[7]_PORT_A_address_reg, E1_q_b[7]_PORT_B_address_reg, E1_q_b[7]_PORT_A_write_enable_reg, E1_q_b[7]_PORT_B_write_enable_reg, , , E1_q_b[7]_clock_0, E1_q_b[7]_clock_1, , , , );
E1_q_b[6] = E1_q_b[7]_PORT_B_data_out[1];


--A1L61 is altera_internal_jtag~TDO at ELA_X0_Y15_N0
A1L61 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);

--A1L71 is altera_internal_jtag~TMSUTAP at ELA_X0_Y15_N0
A1L71 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);

--A1L51 is altera_internal_jtag~TCKUTAP at ELA_X0_Y15_N0
A1L51 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);

--altera_internal_jtag is altera_internal_jtag at ELA_X0_Y15_N0
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);


--P1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X7_Y14_N5
--operation mode is normal

P1_state[5] = AMPP_FUNCTION(!A1L51, P1_state[4], A1L71, P1_state[3], VCC);


--L1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X6_Y11_N0
--operation mode is normal

L1_Q[2] = AMPP_FUNCTION(!A1L51, L3_Q[0], L6_Q[2], L2_Q[2], !C1L2, C1L71);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X9_Y12_N2
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(!A1L51, P1_state[15], C1_jtag_debug_mode, C1L22, C1L32, P1_state[0]);


--L4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X6_Y11_N9
--operation mode is normal

L4_Q[0] = AMPP_FUNCTION(!A1L51, altera_internal_jtag, !C1L2, C1L51);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X8_Y12_N5
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L51, C1L82, N1_dffs[1], C1L92, N1_dffs[0], P1_state[0], P1_state[12]);


--F1L01 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~26 at LC_X8_Y11_N1
--operation mode is normal

F1L01 = AMPP_FUNCTION(L4_Q[0], C1_jtag_debug_mode_usr1, C1_jtag_debug_mode);

--L3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X8_Y11_N1
--operation mode is normal

L3_Q[0] = AMPP_FUNCTION(!A1L51, Q1_dffe1a[1], !C1L2, GND, C1L1);


--F1L2 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LC_X8_Y11_N0
--operation mode is normal

F1L2 = AMPP_FUNCTION(L1_Q[2], F1L01, P1_state[5]);


--F1_ram_rom_data_reg[7] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X8_Y11_N4
--operation mode is normal

F1_ram_rom_data_reg[7] = AMPP_FUNCTION(!A1L51, F1L21, altera_internal_jtag, E1_q_b[7], VCC, F1L71);


--J1_safe_q[0] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[0] at LC_X7_Y11_N0
--operation mode is arithmetic

J1_safe_q[0] = AMPP_FUNCTION(!A1L51, F1_ram_rom_incr_addr, J1_safe_q[0], J1_safe_q[1], !L1_Q[0], F1L11);

--J1L2 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella0~COUT at LC_X7_Y11_N0
--operation mode is arithmetic

J1L2 = AMPP_FUNCTION(J1_safe_q[0]);

--J1L3 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella0~COUTCOUT1_3 at LC_X7_Y11_N0
--operation mode is arithmetic

J1L3 = AMPP_FUNCTION(J1_safe_q[0]);


--J1_safe_q[1] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[1] at LC_X7_Y11_N1
--operation mode is arithmetic

J1_safe_q[1] = AMPP_FUNCTION(!A1L51, F1_ram_rom_incr_addr, J1_safe_q[1], J1_safe_q[2], !L1_Q[0], F1L11, J1L2, J1L3);

--J1L5 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella1~COUT at LC_X7_Y11_N1
--operation mode is arithmetic

J1L5 = AMPP_FUNCTION(J1_safe_q[1], J1L2);

--J1L6 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella1~COUTCOUT1_2 at LC_X7_Y11_N1
--operation mode is arithmetic

J1L6 = AMPP_FUNCTION(J1_safe_q[1], J1L3);


--J1_safe_q[2] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[2] at LC_X7_Y11_N2
--operation mode is arithmetic

J1_safe_q[2] = AMPP_FUNCTION(!A1L51, J1_safe_q[2], F1_ram_rom_incr_addr, J1_safe_q[3], !L1_Q[0], F1L11, J1L5, J1L6);

--J1L8 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella2~COUT at LC_X7_Y11_N2
--operation mode is arithmetic

J1L8 = AMPP_FUNCTION(J1_safe_q[2], J1L5);

--J1L9 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella2~COUTCOUT1_2 at LC_X7_Y11_N2
--operation mode is arithmetic

J1L9 = AMPP_FUNCTION(J1_safe_q[2], J1L6);


--J1_safe_q[3] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[3] at LC_X7_Y11_N3
--operation mode is arithmetic

J1_safe_q[3] = AMPP_FUNCTION(!A1L51, J1_safe_q[3], F1_ram_rom_incr_addr, J1_safe_q[4], !L1_Q[0], F1L11, J1L8, J1L9);

--J1L11 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella3~COUT at LC_X7_Y11_N3
--operation mode is arithmetic

J1L11 = AMPP_FUNCTION(J1_safe_q[3], J1L8);

--J1L21 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella3~COUTCOUT1 at LC_X7_Y11_N3
--operation mode is arithmetic

J1L21 = AMPP_FUNCTION(J1_safe_q[3], J1L9);


--J1_safe_q[4] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[4] at LC_X7_Y11_N4
--operation mode is arithmetic

J1_safe_q[4] = AMPP_FUNCTION(!A1L51, J1_safe_q[4], F1_ram_rom_incr_addr, J1_safe_q[5], !L1_Q[0], F1L11, J1L11, J1L21);

--J1L41 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella4~COUT at LC_X7_Y11_N4
--operation mode is arithmetic

J1L41 = AMPP_FUNCTION(J1_safe_q[4], J1L11, J1L21);


--J1_safe_q[5] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[5] at LC_X7_Y11_N5
--operation mode is arithmetic

J1_safe_q[5] = AMPP_FUNCTION(!A1L51, F1_ram_rom_incr_addr, J1_safe_q[5], J1_safe_q[6], !L1_Q[0], F1L11, J1L41);

--J1L81 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella5~COUT at LC_X7_Y11_N5
--operation mode is arithmetic

J1L81 = AMPP_FUNCTION(J1_safe_q[5]);

--J1L91 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella5~COUTCOUT1_2 at LC_X7_Y11_N5
--operation mode is arithmetic

J1L91 = AMPP_FUNCTION(J1_safe_q[5]);


--J1_safe_q[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[6] at LC_X7_Y11_N6
--operation mode is arithmetic

J1_safe_q[6] = AMPP_FUNCTION(!A1L51, F1_ram_rom_incr_addr, J1_safe_q[6], J1_safe_q[7], !L1_Q[0], F1L11, J1L41, J1L81, J1L91);

--J1L12 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella6~COUT at LC_X7_Y11_N6
--operation mode is arithmetic

J1L12 = AMPP_FUNCTION(J1_safe_q[6], J1L81);

--J1L22 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella6~COUTCOUT1_2 at LC_X7_Y11_N6
--operation mode is arithmetic

J1L22 = AMPP_FUNCTION(J1_safe_q[6], J1L91);


--J1_safe_q[7] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[7] at LC_X7_Y11_N7
--operation mode is normal

J1_safe_q[7] = AMPP_FUNCTION(!A1L51, J1_safe_q[7], A1L11, F1_ram_rom_incr_addr, !L1_Q[0], F1L11, J1L41, J1L12, J1L22);


--F1_ram_rom_data_reg[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] at LC_X9_Y11_N2
--operation mode is normal

F1_ram_rom_data_reg[6] = AMPP_FUNCTION(!A1L51, E1_q_b[6], F1_ram_rom_data_reg[7], F1L21, VCC, F1L71);