lpm_rom0.tan.rpt

s盒设计源程序 可以用语DES设计

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                      ; To                                                                                                                        ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 3.244 ns                         ; address[2]                                                                                                                ; altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 ;                              ; clock                        ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 7.990 ns                         ; altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4]                          ; q[4]                                                                                                                      ; clock                        ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.404 ns                         ; altera_internal_jtag~TDO                                                                                                  ; altera_reserved_tdo                                                                                                       ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.307 ns                         ; altera_internal_jtag~TMSUTAP                                                                                              ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]                                                   ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 175.99 MHz ( period = 5.682 ns ) ; sld_hub:sld_hub_inst|HUB_BYPASS_REG                                                                                       ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                         ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clock'                        ; N/A   ; None          ; 290.87 MHz ( period = 3.438 ns ) ; altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg7 ; altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[7]                          ; clock                        ; clock                        ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                           ;                                                                                                                           ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+