lpm_rom0.map.eqn

s盒设计源程序 可以用语DES设计

E1_q_b[1]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[1]_PORT_B_address_reg = DFFE(E1_q_b[1]_PORT_B_address, E1_q_b[1]_clock_1, , , );
E1_q_b[1]_PORT_A_write_enable = GND;
E1_q_b[1]_PORT_A_write_enable_reg = DFFE(E1_q_b[1]_PORT_A_write_enable, E1_q_b[1]_clock_0, , , );
E1_q_b[1]_PORT_B_write_enable = F1L2;
E1_q_b[1]_PORT_B_write_enable_reg = DFFE(E1_q_b[1]_PORT_B_write_enable, E1_q_b[1]_clock_1, , , );
E1_q_b[1]_clock_0 = clock;
E1_q_b[1]_clock_1 = !A1L51;
E1_q_b[1]_PORT_B_data_out = MEMORY(E1_q_b[1]_PORT_A_data_in_reg, E1_q_b[1]_PORT_B_data_in_reg, E1_q_b[1]_PORT_A_address_reg, E1_q_b[1]_PORT_B_address_reg, E1_q_b[1]_PORT_A_write_enable_reg, E1_q_b[1]_PORT_B_write_enable_reg, , , E1_q_b[1]_clock_0, E1_q_b[1]_clock_1, , , , );
E1_q_b[1] = E1_q_b[1]_PORT_B_data_out[0];


--E1_q_a[0] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[0]_PORT_A_data_in = VCC;
E1_q_a[0]_PORT_A_data_in_reg = DFFE(E1_q_a[0]_PORT_A_data_in, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_PORT_B_data_in = F1_ram_rom_data_reg[0];
E1_q_a[0]_PORT_B_data_in_reg = DFFE(E1_q_a[0]_PORT_B_data_in, E1_q_a[0]_clock_1, , , );
E1_q_a[0]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[0]_PORT_B_address_reg = DFFE(E1_q_a[0]_PORT_B_address, E1_q_a[0]_clock_1, , , );
E1_q_a[0]_PORT_A_write_enable = GND;
E1_q_a[0]_PORT_A_write_enable_reg = DFFE(E1_q_a[0]_PORT_A_write_enable, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_PORT_B_write_enable = F1L2;
E1_q_a[0]_PORT_B_write_enable_reg = DFFE(E1_q_a[0]_PORT_B_write_enable, E1_q_a[0]_clock_1, , , );
E1_q_a[0]_clock_0 = clock;
E1_q_a[0]_clock_1 = !A1L51;
E1_q_a[0]_PORT_A_data_out = MEMORY(E1_q_a[0]_PORT_A_data_in_reg, E1_q_a[0]_PORT_B_data_in_reg, E1_q_a[0]_PORT_A_address_reg, E1_q_a[0]_PORT_B_address_reg, E1_q_a[0]_PORT_A_write_enable_reg, E1_q_a[0]_PORT_B_write_enable_reg, , , E1_q_a[0]_clock_0, E1_q_a[0]_clock_1, , , , );
E1_q_a[0]_PORT_A_data_out_reg = DFFE(E1_q_a[0]_PORT_A_data_out, E1_q_a[0]_clock_0, , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out_reg[0];

--E1_q_b[0] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[0]
E1_q_b[0]_PORT_A_data_in = VCC;
E1_q_b[0]_PORT_A_data_in_reg = DFFE(E1_q_b[0]_PORT_A_data_in, E1_q_b[0]_clock_0, , , );
E1_q_b[0]_PORT_B_data_in = F1_ram_rom_data_reg[0];
E1_q_b[0]_PORT_B_data_in_reg = DFFE(E1_q_b[0]_PORT_B_data_in, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[0]_PORT_A_address_reg = DFFE(E1_q_b[0]_PORT_A_address, E1_q_b[0]_clock_0, , , );
E1_q_b[0]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[0]_PORT_B_address_reg = DFFE(E1_q_b[0]_PORT_B_address, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_PORT_A_write_enable = GND;
E1_q_b[0]_PORT_A_write_enable_reg = DFFE(E1_q_b[0]_PORT_A_write_enable, E1_q_b[0]_clock_0, , , );
E1_q_b[0]_PORT_B_write_enable = F1L2;
E1_q_b[0]_PORT_B_write_enable_reg = DFFE(E1_q_b[0]_PORT_B_write_enable, E1_q_b[0]_clock_1, , , );
E1_q_b[0]_clock_0 = clock;
E1_q_b[0]_clock_1 = !A1L51;
E1_q_b[0]_PORT_B_data_out = MEMORY(E1_q_b[0]_PORT_A_data_in_reg, E1_q_b[0]_PORT_B_data_in_reg, E1_q_b[0]_PORT_A_address_reg, E1_q_b[0]_PORT_B_address_reg, E1_q_b[0]_PORT_A_write_enable_reg, E1_q_b[0]_PORT_B_write_enable_reg, , , E1_q_b[0]_clock_0, E1_q_b[0]_clock_1, , , , );
E1_q_b[0] = E1_q_b[0]_PORT_B_data_out[0];


--A1L61 is altera_internal_jtag~TDO
A1L61 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);

--A1L71 is altera_internal_jtag~TMSUTAP
A1L71 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);

--A1L51 is altera_internal_jtag~TCKUTAP
A1L51 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1L41Q);


--P1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

P1_state[5] = AMPP_FUNCTION(!A1L51, P1_state[4], P1_state[3], A1L71, VCC);


--L1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

L1_Q[2] = AMPP_FUNCTION(!A1L51, L2_Q[2], L6_Q[2], L3_Q[0], !C1L2, C1L71);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(!A1L51, C1L22, C1_jtag_debug_mode, C1L32, P1_state[15], P1_state[0]);


--L4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

L4_Q[0] = AMPP_FUNCTION(!A1L51, altera_internal_jtag, !C1L2, C1L51);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L51, N1_dffs[0], N1_dffs[1], C1L82, C1L92, P1_state[0], P1_state[12]);


--L3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

L3_Q[0] = AMPP_FUNCTION(!A1L51, Q1_dffe1a[1], !C1L2, C1L1);


--F1L01 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~26
--operation mode is normal

F1L01 = AMPP_FUNCTION(C1_jtag_debug_mode, L4_Q[0], C1_jtag_debug_mode_usr1, L3_Q[0]);


--F1L2 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
--operation mode is normal

F1L2 = AMPP_FUNCTION(P1_state[5], L1_Q[2], F1L01);


--F1_ram_rom_data_reg[7] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

F1_ram_rom_data_reg[7] = AMPP_FUNCTION(!A1L51, E1_q_b[7], F1L21, altera_internal_jtag, VCC, F1L71);


--J1_safe_q[0] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[0]
--operation mode is arithmetic

J1_safe_q[0] = AMPP_FUNCTION(!A1L51, J1_safe_q[0], F1_ram_rom_incr_addr, J1_safe_q[1], !L1_Q[0], F1L11);

--J1L2 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

J1L2 = AMPP_FUNCTION(J1_safe_q[0]);


--J1_safe_q[1] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[1]
--operation mode is arithmetic

J1_safe_q[1] = AMPP_FUNCTION(!A1L51, J1_safe_q[1], F1_ram_rom_incr_addr, J1_safe_q[2], !L1_Q[0], F1L11, J1L2);

--J1L4 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

J1L4 = AMPP_FUNCTION(J1_safe_q[1], J1L2);


--J1_safe_q[2] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[2]
--operation mode is arithmetic

J1_safe_q[2] = AMPP_FUNCTION(!A1L51, J1_safe_q[2], F1_ram_rom_incr_addr, J1_safe_q[3], !L1_Q[0], F1L11, J1L4);

--J1L6 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

J1L6 = AMPP_FUNCTION(J1_safe_q[2], J1L4);


--J1_safe_q[3] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[3]
--operation mode is arithmetic

J1_safe_q[3] = AMPP_FUNCTION(!A1L51, J1_safe_q[3], F1_ram_rom_incr_addr, J1_safe_q[4], !L1_Q[0], F1L11, J1L6);

--J1L8 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

J1L8 = AMPP_FUNCTION(J1_safe_q[3], J1L6);


--J1_safe_q[4] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[4]
--operation mode is arithmetic

J1_safe_q[4] = AMPP_FUNCTION(!A1L51, J1_safe_q[4], F1_ram_rom_incr_addr, J1_safe_q[5], !L1_Q[0], F1L11, J1L8);

--J1L01 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

J1L01 = AMPP_FUNCTION(J1_safe_q[4], J1L8);


--J1_safe_q[5] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[5]
--operation mode is arithmetic

J1_safe_q[5] = AMPP_FUNCTION(!A1L51, J1_safe_q[5], F1_ram_rom_incr_addr, J1_safe_q[6], !L1_Q[0], F1L11, J1L01);

--J1L21 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

J1L21 = AMPP_FUNCTION(J1_safe_q[5], J1L01);


--J1_safe_q[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[6]
--operation mode is arithmetic

J1_safe_q[6] = AMPP_FUNCTION(!A1L51, J1_safe_q[6], F1_ram_rom_incr_addr, J1_safe_q[7], !L1_Q[0], F1L11, J1L21);

--J1L41 is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

J1L41 = AMPP_FUNCTION(J1_safe_q[6], J1L21);


--J1_safe_q[7] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated|safe_q[7]
--operation mode is normal

J1_safe_q[7] = AMPP_FUNCTION(!A1L51, J1_safe_q[7], F1_ram_rom_incr_addr, A1L11, !L1_Q[0], F1L11, J1L41);


--F1_ram_rom_data_reg[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

F1_ram_rom_data_reg[6] = AMPP_FUNCTION(!A1L51, E1_q_b[6], F1_ram_rom_data_reg[7], F1L21, VCC, F1L71);


--F1_ram_rom_data_reg[5] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

F1_ram_rom_data_reg[5] = AMPP_FUNCTION(!A1L51, E1_q_b[5], F1_ram_rom_data_reg[6], F1L21, VCC, F1L71);


--F1_ram_rom_data_reg[4] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

F1_ram_rom_data_reg[4] = AMPP_FUNCTION(!A1L51, E1_q_b[4], F1_ram_rom_data_reg[5], F1L21, VCC, F1L71);


--F1_ram_rom_data_reg[3] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

F1_ram_rom_data_reg[3] = AMPP_FUNCTION(!A1L51, E1_q_b[3], F1_ram_rom_data_reg[4], F1L21, VCC, F1L71);


--F1_ram_rom_data_reg[2] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal

F1_ram_rom_data_reg[2] = AMPP_FUNCTION(!A1L51, E1_q_b[2], F1_ram_rom_data_reg[3], F1L21, VCC, F1L71);


--F1_ram_rom_data_reg[1] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

F1_ram_rom_data_reg[1] = AMPP_FUNCTION(!A1L51, E1_q_b[1], F1_ram_rom_data_reg[2], F1L21, VCC, F1L71);


--F1_ram_rom_data_reg[0] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

F1_ram_rom_data_reg[0] = AMPP_FUNCTION(!A1L51, E1_q_b[0], F1_ram_rom_data_reg[1], F1L21, VCC, F1L71);


--C1L41Q is sld_hub:sld_hub_inst|HUB_TDO~reg0
--operation mode is normal

C1L41Q = AMPP_FUNCTION(A1L51, C1_jtag_debug_mode_usr1, L6_Q[0], C1L11, C1L21, !P1_state[8], C1L72);


--P1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
--operation mode is normal

P1_state[4] = AMPP_FUNCTION(!A1L51, P1_state[3], P1_state[4], P1_state[7], VCC, !A1L71);


--P1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
--operation mode is normal

P1_state[3] = AMPP_FUNCTION(!A1L51, A1L71, P1_state[2], VCC);


--L2_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

L2_Q[2] = AMPP_FUNCTION(!A1L51, L6_Q[2], !C1L2, C1L8);


--L6_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

L6_Q[2] = AMPP_FUNCTION(!A1L51, L6_Q[3], F1_ir_loaded_address_reg[1], P1_state[4], !C1L2, L6L4);


--P1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
--operation mode is normal

P1_state[1] = AMPP_FUNCTION(!A1L51, P1_state[0], P1_state[1], P1_state[8], P1_state[15], VCC, !A1L71);