lpm_rom0.map.eqn

s盒设计源程序 可以用语DES设计

--E1_q_a[7] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[7]_PORT_A_data_in = VCC;
E1_q_a[7]_PORT_A_data_in_reg = DFFE(E1_q_a[7]_PORT_A_data_in, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_PORT_B_data_in = F1_ram_rom_data_reg[7];
E1_q_a[7]_PORT_B_data_in_reg = DFFE(E1_q_a[7]_PORT_B_data_in, E1_q_a[7]_clock_1, , , );
E1_q_a[7]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[7]_PORT_B_address_reg = DFFE(E1_q_a[7]_PORT_B_address, E1_q_a[7]_clock_1, , , );
E1_q_a[7]_PORT_A_write_enable = GND;
E1_q_a[7]_PORT_A_write_enable_reg = DFFE(E1_q_a[7]_PORT_A_write_enable, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_PORT_B_write_enable = F1L2;
E1_q_a[7]_PORT_B_write_enable_reg = DFFE(E1_q_a[7]_PORT_B_write_enable, E1_q_a[7]_clock_1, , , );
E1_q_a[7]_clock_0 = clock;
E1_q_a[7]_clock_1 = !A1L51;
E1_q_a[7]_PORT_A_data_out = MEMORY(E1_q_a[7]_PORT_A_data_in_reg, E1_q_a[7]_PORT_B_data_in_reg, E1_q_a[7]_PORT_A_address_reg, E1_q_a[7]_PORT_B_address_reg, E1_q_a[7]_PORT_A_write_enable_reg, E1_q_a[7]_PORT_B_write_enable_reg, , , E1_q_a[7]_clock_0, E1_q_a[7]_clock_1, , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out_reg[0];

--E1_q_b[7] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[7]
E1_q_b[7]_PORT_A_data_in = VCC;
E1_q_b[7]_PORT_A_data_in_reg = DFFE(E1_q_b[7]_PORT_A_data_in, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_data_in = F1_ram_rom_data_reg[7];
E1_q_b[7]_PORT_B_data_in_reg = DFFE(E1_q_b[7]_PORT_B_data_in, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[7]_PORT_A_address_reg = DFFE(E1_q_b[7]_PORT_A_address, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[7]_PORT_B_address_reg = DFFE(E1_q_b[7]_PORT_B_address, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_PORT_A_write_enable = GND;
E1_q_b[7]_PORT_A_write_enable_reg = DFFE(E1_q_b[7]_PORT_A_write_enable, E1_q_b[7]_clock_0, , , );
E1_q_b[7]_PORT_B_write_enable = F1L2;
E1_q_b[7]_PORT_B_write_enable_reg = DFFE(E1_q_b[7]_PORT_B_write_enable, E1_q_b[7]_clock_1, , , );
E1_q_b[7]_clock_0 = clock;
E1_q_b[7]_clock_1 = !A1L51;
E1_q_b[7]_PORT_B_data_out = MEMORY(E1_q_b[7]_PORT_A_data_in_reg, E1_q_b[7]_PORT_B_data_in_reg, E1_q_b[7]_PORT_A_address_reg, E1_q_b[7]_PORT_B_address_reg, E1_q_b[7]_PORT_A_write_enable_reg, E1_q_b[7]_PORT_B_write_enable_reg, , , E1_q_b[7]_clock_0, E1_q_b[7]_clock_1, , , , );
E1_q_b[7] = E1_q_b[7]_PORT_B_data_out[0];


--E1_q_a[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[6]_PORT_A_data_in = VCC;
E1_q_a[6]_PORT_A_data_in_reg = DFFE(E1_q_a[6]_PORT_A_data_in, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_PORT_B_data_in = F1_ram_rom_data_reg[6];
E1_q_a[6]_PORT_B_data_in_reg = DFFE(E1_q_a[6]_PORT_B_data_in, E1_q_a[6]_clock_1, , , );
E1_q_a[6]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[6]_PORT_B_address_reg = DFFE(E1_q_a[6]_PORT_B_address, E1_q_a[6]_clock_1, , , );
E1_q_a[6]_PORT_A_write_enable = GND;
E1_q_a[6]_PORT_A_write_enable_reg = DFFE(E1_q_a[6]_PORT_A_write_enable, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_PORT_B_write_enable = F1L2;
E1_q_a[6]_PORT_B_write_enable_reg = DFFE(E1_q_a[6]_PORT_B_write_enable, E1_q_a[6]_clock_1, , , );
E1_q_a[6]_clock_0 = clock;
E1_q_a[6]_clock_1 = !A1L51;
E1_q_a[6]_PORT_A_data_out = MEMORY(E1_q_a[6]_PORT_A_data_in_reg, E1_q_a[6]_PORT_B_data_in_reg, E1_q_a[6]_PORT_A_address_reg, E1_q_a[6]_PORT_B_address_reg, E1_q_a[6]_PORT_A_write_enable_reg, E1_q_a[6]_PORT_B_write_enable_reg, , , E1_q_a[6]_clock_0, E1_q_a[6]_clock_1, , , , );
E1_q_a[6]_PORT_A_data_out_reg = DFFE(E1_q_a[6]_PORT_A_data_out, E1_q_a[6]_clock_0, , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out_reg[0];

--E1_q_b[6] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[6]
E1_q_b[6]_PORT_A_data_in = VCC;
E1_q_b[6]_PORT_A_data_in_reg = DFFE(E1_q_b[6]_PORT_A_data_in, E1_q_b[6]_clock_0, , , );
E1_q_b[6]_PORT_B_data_in = F1_ram_rom_data_reg[6];
E1_q_b[6]_PORT_B_data_in_reg = DFFE(E1_q_b[6]_PORT_B_data_in, E1_q_b[6]_clock_1, , , );
E1_q_b[6]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[6]_PORT_A_address_reg = DFFE(E1_q_b[6]_PORT_A_address, E1_q_b[6]_clock_0, , , );
E1_q_b[6]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[6]_PORT_B_address_reg = DFFE(E1_q_b[6]_PORT_B_address, E1_q_b[6]_clock_1, , , );
E1_q_b[6]_PORT_A_write_enable = GND;
E1_q_b[6]_PORT_A_write_enable_reg = DFFE(E1_q_b[6]_PORT_A_write_enable, E1_q_b[6]_clock_0, , , );
E1_q_b[6]_PORT_B_write_enable = F1L2;
E1_q_b[6]_PORT_B_write_enable_reg = DFFE(E1_q_b[6]_PORT_B_write_enable, E1_q_b[6]_clock_1, , , );
E1_q_b[6]_clock_0 = clock;
E1_q_b[6]_clock_1 = !A1L51;
E1_q_b[6]_PORT_B_data_out = MEMORY(E1_q_b[6]_PORT_A_data_in_reg, E1_q_b[6]_PORT_B_data_in_reg, E1_q_b[6]_PORT_A_address_reg, E1_q_b[6]_PORT_B_address_reg, E1_q_b[6]_PORT_A_write_enable_reg, E1_q_b[6]_PORT_B_write_enable_reg, , , E1_q_b[6]_clock_0, E1_q_b[6]_clock_1, , , , );
E1_q_b[6] = E1_q_b[6]_PORT_B_data_out[0];


--E1_q_a[5] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[5]_PORT_A_data_in = VCC;
E1_q_a[5]_PORT_A_data_in_reg = DFFE(E1_q_a[5]_PORT_A_data_in, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_PORT_B_data_in = F1_ram_rom_data_reg[5];
E1_q_a[5]_PORT_B_data_in_reg = DFFE(E1_q_a[5]_PORT_B_data_in, E1_q_a[5]_clock_1, , , );
E1_q_a[5]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[5]_PORT_B_address_reg = DFFE(E1_q_a[5]_PORT_B_address, E1_q_a[5]_clock_1, , , );
E1_q_a[5]_PORT_A_write_enable = GND;
E1_q_a[5]_PORT_A_write_enable_reg = DFFE(E1_q_a[5]_PORT_A_write_enable, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_PORT_B_write_enable = F1L2;
E1_q_a[5]_PORT_B_write_enable_reg = DFFE(E1_q_a[5]_PORT_B_write_enable, E1_q_a[5]_clock_1, , , );
E1_q_a[5]_clock_0 = clock;
E1_q_a[5]_clock_1 = !A1L51;
E1_q_a[5]_PORT_A_data_out = MEMORY(E1_q_a[5]_PORT_A_data_in_reg, E1_q_a[5]_PORT_B_data_in_reg, E1_q_a[5]_PORT_A_address_reg, E1_q_a[5]_PORT_B_address_reg, E1_q_a[5]_PORT_A_write_enable_reg, E1_q_a[5]_PORT_B_write_enable_reg, , , E1_q_a[5]_clock_0, E1_q_a[5]_clock_1, , , , );
E1_q_a[5]_PORT_A_data_out_reg = DFFE(E1_q_a[5]_PORT_A_data_out, E1_q_a[5]_clock_0, , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out_reg[0];

--E1_q_b[5] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[5]
E1_q_b[5]_PORT_A_data_in = VCC;
E1_q_b[5]_PORT_A_data_in_reg = DFFE(E1_q_b[5]_PORT_A_data_in, E1_q_b[5]_clock_0, , , );
E1_q_b[5]_PORT_B_data_in = F1_ram_rom_data_reg[5];
E1_q_b[5]_PORT_B_data_in_reg = DFFE(E1_q_b[5]_PORT_B_data_in, E1_q_b[5]_clock_1, , , );
E1_q_b[5]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[5]_PORT_A_address_reg = DFFE(E1_q_b[5]_PORT_A_address, E1_q_b[5]_clock_0, , , );
E1_q_b[5]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[5]_PORT_B_address_reg = DFFE(E1_q_b[5]_PORT_B_address, E1_q_b[5]_clock_1, , , );
E1_q_b[5]_PORT_A_write_enable = GND;
E1_q_b[5]_PORT_A_write_enable_reg = DFFE(E1_q_b[5]_PORT_A_write_enable, E1_q_b[5]_clock_0, , , );
E1_q_b[5]_PORT_B_write_enable = F1L2;
E1_q_b[5]_PORT_B_write_enable_reg = DFFE(E1_q_b[5]_PORT_B_write_enable, E1_q_b[5]_clock_1, , , );
E1_q_b[5]_clock_0 = clock;
E1_q_b[5]_clock_1 = !A1L51;
E1_q_b[5]_PORT_B_data_out = MEMORY(E1_q_b[5]_PORT_A_data_in_reg, E1_q_b[5]_PORT_B_data_in_reg, E1_q_b[5]_PORT_A_address_reg, E1_q_b[5]_PORT_B_address_reg, E1_q_b[5]_PORT_A_write_enable_reg, E1_q_b[5]_PORT_B_write_enable_reg, , , E1_q_b[5]_clock_0, E1_q_b[5]_clock_1, , , , );
E1_q_b[5] = E1_q_b[5]_PORT_B_data_out[0];


--E1_q_a[4] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[4]_PORT_A_data_in = VCC;
E1_q_a[4]_PORT_A_data_in_reg = DFFE(E1_q_a[4]_PORT_A_data_in, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_PORT_B_data_in = F1_ram_rom_data_reg[4];
E1_q_a[4]_PORT_B_data_in_reg = DFFE(E1_q_a[4]_PORT_B_data_in, E1_q_a[4]_clock_1, , , );
E1_q_a[4]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[4]_PORT_B_address_reg = DFFE(E1_q_a[4]_PORT_B_address, E1_q_a[4]_clock_1, , , );
E1_q_a[4]_PORT_A_write_enable = GND;
E1_q_a[4]_PORT_A_write_enable_reg = DFFE(E1_q_a[4]_PORT_A_write_enable, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_PORT_B_write_enable = F1L2;
E1_q_a[4]_PORT_B_write_enable_reg = DFFE(E1_q_a[4]_PORT_B_write_enable, E1_q_a[4]_clock_1, , , );
E1_q_a[4]_clock_0 = clock;
E1_q_a[4]_clock_1 = !A1L51;
E1_q_a[4]_PORT_A_data_out = MEMORY(E1_q_a[4]_PORT_A_data_in_reg, E1_q_a[4]_PORT_B_data_in_reg, E1_q_a[4]_PORT_A_address_reg, E1_q_a[4]_PORT_B_address_reg, E1_q_a[4]_PORT_A_write_enable_reg, E1_q_a[4]_PORT_B_write_enable_reg, , , E1_q_a[4]_clock_0, E1_q_a[4]_clock_1, , , , );
E1_q_a[4]_PORT_A_data_out_reg = DFFE(E1_q_a[4]_PORT_A_data_out, E1_q_a[4]_clock_0, , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out_reg[0];

--E1_q_b[4] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[4]
E1_q_b[4]_PORT_A_data_in = VCC;
E1_q_b[4]_PORT_A_data_in_reg = DFFE(E1_q_b[4]_PORT_A_data_in, E1_q_b[4]_clock_0, , , );
E1_q_b[4]_PORT_B_data_in = F1_ram_rom_data_reg[4];
E1_q_b[4]_PORT_B_data_in_reg = DFFE(E1_q_b[4]_PORT_B_data_in, E1_q_b[4]_clock_1, , , );
E1_q_b[4]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[4]_PORT_A_address_reg = DFFE(E1_q_b[4]_PORT_A_address, E1_q_b[4]_clock_0, , , );
E1_q_b[4]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[4]_PORT_B_address_reg = DFFE(E1_q_b[4]_PORT_B_address, E1_q_b[4]_clock_1, , , );
E1_q_b[4]_PORT_A_write_enable = GND;
E1_q_b[4]_PORT_A_write_enable_reg = DFFE(E1_q_b[4]_PORT_A_write_enable, E1_q_b[4]_clock_0, , , );
E1_q_b[4]_PORT_B_write_enable = F1L2;
E1_q_b[4]_PORT_B_write_enable_reg = DFFE(E1_q_b[4]_PORT_B_write_enable, E1_q_b[4]_clock_1, , , );
E1_q_b[4]_clock_0 = clock;
E1_q_b[4]_clock_1 = !A1L51;
E1_q_b[4]_PORT_B_data_out = MEMORY(E1_q_b[4]_PORT_A_data_in_reg, E1_q_b[4]_PORT_B_data_in_reg, E1_q_b[4]_PORT_A_address_reg, E1_q_b[4]_PORT_B_address_reg, E1_q_b[4]_PORT_A_write_enable_reg, E1_q_b[4]_PORT_B_write_enable_reg, , , E1_q_b[4]_clock_0, E1_q_b[4]_clock_1, , , , );
E1_q_b[4] = E1_q_b[4]_PORT_B_data_out[0];


--E1_q_a[3] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[3]_PORT_A_data_in = VCC;
E1_q_a[3]_PORT_A_data_in_reg = DFFE(E1_q_a[3]_PORT_A_data_in, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_PORT_B_data_in = F1_ram_rom_data_reg[3];
E1_q_a[3]_PORT_B_data_in_reg = DFFE(E1_q_a[3]_PORT_B_data_in, E1_q_a[3]_clock_1, , , );
E1_q_a[3]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[3]_PORT_B_address_reg = DFFE(E1_q_a[3]_PORT_B_address, E1_q_a[3]_clock_1, , , );
E1_q_a[3]_PORT_A_write_enable = GND;
E1_q_a[3]_PORT_A_write_enable_reg = DFFE(E1_q_a[3]_PORT_A_write_enable, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_PORT_B_write_enable = F1L2;
E1_q_a[3]_PORT_B_write_enable_reg = DFFE(E1_q_a[3]_PORT_B_write_enable, E1_q_a[3]_clock_1, , , );
E1_q_a[3]_clock_0 = clock;
E1_q_a[3]_clock_1 = !A1L51;
E1_q_a[3]_PORT_A_data_out = MEMORY(E1_q_a[3]_PORT_A_data_in_reg, E1_q_a[3]_PORT_B_data_in_reg, E1_q_a[3]_PORT_A_address_reg, E1_q_a[3]_PORT_B_address_reg, E1_q_a[3]_PORT_A_write_enable_reg, E1_q_a[3]_PORT_B_write_enable_reg, , , E1_q_a[3]_clock_0, E1_q_a[3]_clock_1, , , , );
E1_q_a[3]_PORT_A_data_out_reg = DFFE(E1_q_a[3]_PORT_A_data_out, E1_q_a[3]_clock_0, , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out_reg[0];

--E1_q_b[3] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[3]
E1_q_b[3]_PORT_A_data_in = VCC;
E1_q_b[3]_PORT_A_data_in_reg = DFFE(E1_q_b[3]_PORT_A_data_in, E1_q_b[3]_clock_0, , , );
E1_q_b[3]_PORT_B_data_in = F1_ram_rom_data_reg[3];
E1_q_b[3]_PORT_B_data_in_reg = DFFE(E1_q_b[3]_PORT_B_data_in, E1_q_b[3]_clock_1, , , );
E1_q_b[3]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[3]_PORT_A_address_reg = DFFE(E1_q_b[3]_PORT_A_address, E1_q_b[3]_clock_0, , , );
E1_q_b[3]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[3]_PORT_B_address_reg = DFFE(E1_q_b[3]_PORT_B_address, E1_q_b[3]_clock_1, , , );
E1_q_b[3]_PORT_A_write_enable = GND;
E1_q_b[3]_PORT_A_write_enable_reg = DFFE(E1_q_b[3]_PORT_A_write_enable, E1_q_b[3]_clock_0, , , );
E1_q_b[3]_PORT_B_write_enable = F1L2;
E1_q_b[3]_PORT_B_write_enable_reg = DFFE(E1_q_b[3]_PORT_B_write_enable, E1_q_b[3]_clock_1, , , );
E1_q_b[3]_clock_0 = clock;
E1_q_b[3]_clock_1 = !A1L51;
E1_q_b[3]_PORT_B_data_out = MEMORY(E1_q_b[3]_PORT_A_data_in_reg, E1_q_b[3]_PORT_B_data_in_reg, E1_q_b[3]_PORT_A_address_reg, E1_q_b[3]_PORT_B_address_reg, E1_q_b[3]_PORT_A_write_enable_reg, E1_q_b[3]_PORT_B_write_enable_reg, , , E1_q_b[3]_clock_0, E1_q_b[3]_clock_1, , , , );
E1_q_b[3] = E1_q_b[3]_PORT_B_data_out[0];


--E1_q_a[2] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[2]_PORT_A_data_in = VCC;
E1_q_a[2]_PORT_A_data_in_reg = DFFE(E1_q_a[2]_PORT_A_data_in, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_PORT_B_data_in = F1_ram_rom_data_reg[2];
E1_q_a[2]_PORT_B_data_in_reg = DFFE(E1_q_a[2]_PORT_B_data_in, E1_q_a[2]_clock_1, , , );
E1_q_a[2]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[2]_PORT_B_address_reg = DFFE(E1_q_a[2]_PORT_B_address, E1_q_a[2]_clock_1, , , );
E1_q_a[2]_PORT_A_write_enable = GND;
E1_q_a[2]_PORT_A_write_enable_reg = DFFE(E1_q_a[2]_PORT_A_write_enable, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_PORT_B_write_enable = F1L2;
E1_q_a[2]_PORT_B_write_enable_reg = DFFE(E1_q_a[2]_PORT_B_write_enable, E1_q_a[2]_clock_1, , , );
E1_q_a[2]_clock_0 = clock;
E1_q_a[2]_clock_1 = !A1L51;
E1_q_a[2]_PORT_A_data_out = MEMORY(E1_q_a[2]_PORT_A_data_in_reg, E1_q_a[2]_PORT_B_data_in_reg, E1_q_a[2]_PORT_A_address_reg, E1_q_a[2]_PORT_B_address_reg, E1_q_a[2]_PORT_A_write_enable_reg, E1_q_a[2]_PORT_B_write_enable_reg, , , E1_q_a[2]_clock_0, E1_q_a[2]_clock_1, , , , );
E1_q_a[2]_PORT_A_data_out_reg = DFFE(E1_q_a[2]_PORT_A_data_out, E1_q_a[2]_clock_0, , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out_reg[0];

--E1_q_b[2] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[2]
E1_q_b[2]_PORT_A_data_in = VCC;
E1_q_b[2]_PORT_A_data_in_reg = DFFE(E1_q_b[2]_PORT_A_data_in, E1_q_b[2]_clock_0, , , );
E1_q_b[2]_PORT_B_data_in = F1_ram_rom_data_reg[2];
E1_q_b[2]_PORT_B_data_in_reg = DFFE(E1_q_b[2]_PORT_B_data_in, E1_q_b[2]_clock_1, , , );
E1_q_b[2]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[2]_PORT_A_address_reg = DFFE(E1_q_b[2]_PORT_A_address, E1_q_b[2]_clock_0, , , );
E1_q_b[2]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_b[2]_PORT_B_address_reg = DFFE(E1_q_b[2]_PORT_B_address, E1_q_b[2]_clock_1, , , );
E1_q_b[2]_PORT_A_write_enable = GND;
E1_q_b[2]_PORT_A_write_enable_reg = DFFE(E1_q_b[2]_PORT_A_write_enable, E1_q_b[2]_clock_0, , , );
E1_q_b[2]_PORT_B_write_enable = F1L2;
E1_q_b[2]_PORT_B_write_enable_reg = DFFE(E1_q_b[2]_PORT_B_write_enable, E1_q_b[2]_clock_1, , , );
E1_q_b[2]_clock_0 = clock;
E1_q_b[2]_clock_1 = !A1L51;
E1_q_b[2]_PORT_B_data_out = MEMORY(E1_q_b[2]_PORT_A_data_in_reg, E1_q_b[2]_PORT_B_data_in_reg, E1_q_b[2]_PORT_A_address_reg, E1_q_b[2]_PORT_B_address_reg, E1_q_b[2]_PORT_A_write_enable_reg, E1_q_b[2]_PORT_B_write_enable_reg, , , E1_q_b[2]_clock_0, E1_q_b[2]_clock_1, , , , );
E1_q_b[2] = E1_q_b[2]_PORT_B_data_out[0];


--E1_q_a[1] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
E1_q_a[1]_PORT_A_data_in = VCC;
E1_q_a[1]_PORT_A_data_in_reg = DFFE(E1_q_a[1]_PORT_A_data_in, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_PORT_B_data_in = F1_ram_rom_data_reg[1];
E1_q_a[1]_PORT_B_data_in_reg = DFFE(E1_q_a[1]_PORT_B_data_in, E1_q_a[1]_clock_1, , , );
E1_q_a[1]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_PORT_B_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7]);
E1_q_a[1]_PORT_B_address_reg = DFFE(E1_q_a[1]_PORT_B_address, E1_q_a[1]_clock_1, , , );
E1_q_a[1]_PORT_A_write_enable = GND;
E1_q_a[1]_PORT_A_write_enable_reg = DFFE(E1_q_a[1]_PORT_A_write_enable, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_PORT_B_write_enable = F1L2;
E1_q_a[1]_PORT_B_write_enable_reg = DFFE(E1_q_a[1]_PORT_B_write_enable, E1_q_a[1]_clock_1, , , );
E1_q_a[1]_clock_0 = clock;
E1_q_a[1]_clock_1 = !A1L51;
E1_q_a[1]_PORT_A_data_out = MEMORY(E1_q_a[1]_PORT_A_data_in_reg, E1_q_a[1]_PORT_B_data_in_reg, E1_q_a[1]_PORT_A_address_reg, E1_q_a[1]_PORT_B_address_reg, E1_q_a[1]_PORT_A_write_enable_reg, E1_q_a[1]_PORT_B_write_enable_reg, , , E1_q_a[1]_clock_0, E1_q_a[1]_clock_1, , , , );
E1_q_a[1]_PORT_A_data_out_reg = DFFE(E1_q_a[1]_PORT_A_data_out, E1_q_a[1]_clock_0, , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out_reg[0];

--E1_q_b[1] is altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_b[1]
E1_q_b[1]_PORT_A_data_in = VCC;
E1_q_b[1]_PORT_A_data_in_reg = DFFE(E1_q_b[1]_PORT_A_data_in, E1_q_b[1]_clock_0, , , );
E1_q_b[1]_PORT_B_data_in = F1_ram_rom_data_reg[1];
E1_q_b[1]_PORT_B_data_in_reg = DFFE(E1_q_b[1]_PORT_B_data_in, E1_q_b[1]_clock_1, , , );
E1_q_b[1]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7]);
E1_q_b[1]_PORT_A_address_reg = DFFE(E1_q_b[1]_PORT_A_address, E1_q_b[1]_clock_0, , , );