lpm_rom0.fit.qmsg

s盒设计源程序 可以用语DES设计

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.360 ns register register " "Info: Estimated most critical path is register to register delay of 2.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 1 REG LAB_X7_Y12 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y12; Fanout = 32; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.366 ns) 0.526 ns sld_hub:sld_hub_inst\|process12~0 2 COMB LAB_X7_Y12 1 " "Info: 2: + IC(0.160 ns) + CELL(0.366 ns) = 0.526 ns; Loc. = LAB_X7_Y12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|process12~0'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "0.526 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|process12~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.705 ns) 2.360 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 3 REG LAB_X9_Y11 0 " "Info: 3: + IC(1.129 ns) + CELL(0.705 ns) = 2.360 ns; Loc. = LAB_X9_Y11; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "1.834 ns" { sld_hub:sld_hub_inst|process12~0 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.071 ns 45.38 % " "Info: Total cell delay = 1.071 ns ( 45.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.289 ns 54.62 % " "Info: Total interconnect delay = 1.289 ns ( 54.62 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.360 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|process12~0 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] -- routed using non-global resources" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] -- routed using non-global resources" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\]" } } } } { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] -- routed using non-global resources" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\]" } } } } { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] -- routed using non-global resources" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] -- routed using non-global resources" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\]" } } } } { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out " "Info: Port clear -- assigned as a global for destination node altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out -- routed using non-global resources" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out" } } } } { "sld_mod_ram_rom.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" 692 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out } "NODE_NAME" } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" { Floorplan "E:/weiling work/lpm/s_box/lpm_rom0.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 25 23:47:45 2005 " "Info: Processing ended: Sun Dec 25 23:47:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}