lpm_rom0.map.qmsg

s盒设计源程序 可以用语DES设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 25 23:47:23 2005 " "Info: Processing started: Sun Dec 25 23:47:23 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off lpm_rom0 -c lpm_rom0 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lpm_rom0 -c lpm_rom0" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_rom0.vhd 2 1 " "Info: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0-SYN " "Info: Found design unit 1: lpm_rom0-SYN" {  } { { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/quartus2/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_95s.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_95s.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_95s " "Info: Found entity 1: altsyncram_95s" {  } { { "db/altsyncram_95s.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_95s.tdf" 33 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3s92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3s92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3s92 " "Info: Found entity 1: altsyncram_3s92" {  } { { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "sld_mod_ram_rom.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "sld_mod_ram_rom.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "sld_mod_ram_rom.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../quartus2/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "e:/quartus2/libraries/megafunctions/lpm_shiftreg.tdf" 43 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "e:/quartus2/libraries/megafunctions/lpm_decode.tdf" 68 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_bje.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_bje.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_bje " "Info: Found entity 1: decode_bje" {  } { { "db/decode_bje.tdf" "" { Text "E:/weiling work/lpm/s_box/db/decode_bje.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~56 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~56\"" {  } { { "sld_mod_ram_rom.vhd" "ram_rom_addr_reg\[0\]~56" { Text "e:/quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" 394 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~12 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~12\"" {  } { { "sld_mod_ram_rom.vhd" "ram_rom_data_shift_cntr_reg\[0\]~12" { Text "e:/quartus2/libraries/megafunctions/sld_mod_ram_rom.vhd" 511 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus2/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus2/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "e:/quartus2/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ov8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_ov8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ov8 " "Info: Found entity 1: cntr_ov8" {  } { { "db/cntr_ov8.tdf" "" { Text "E:/weiling work/lpm/s_box/db/cntr_ov8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_re8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_re8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_re8 " "Info: Found entity 1: cntr_re8" {  } { { "db/cntr_re8.tdf" "" { Text "E:/weiling work/lpm/s_box/db/cntr_re8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "191 " "Info: Implemented 191 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "160 " "Info: Implemented 160 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 25 23:47:30 2005 " "Info: Processing ended: Sun Dec 25 23:47:30 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}