altsyncram_95s.tdf

s盒设计源程序 可以用语DES设计

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" ENABLE_RUNTIME_MOD="YES" INIT_FILE="lpm_rom0.mif" INSTANCE_NAME="NONE" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a
--VERSION_BEGIN 4.2 cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


FUNCTION altsyncram_3s92 (address_a[7..0], address_b[7..0], clock0, clock1, data_b[7..0], wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);
FUNCTION sld_mod_ram_rom (data_read[7..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[7..0], data_write[7..0], enable_write, tck_usr);

--synthesis_resources = ram_bits (auto) 2048 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_95s
( 
	address_a[7..0]	:	input;
	clock0	:	input;
	q_a[7..0]	:	output;
) 
VARIABLE 
	altsyncram1 : altsyncram_3s92;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 0,
			NUMWORDS = 256,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 8,
			WIDTHAD = 8
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE